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9070466 Mismatch error reduction method and system for STT MRAM  
The invention relates to methods and systems for reading a memory cell and in particular, an STT MRAM. In accordance with one aspect of the invention, a method for reading a memory cell includes...
9042185 Row driver circuit for NAND memories including a decoupling inverter  
Devices, methods, and circuits for row driver architectures that can improve an existing row driver circuit including a boosting capacitor and a level shifter circuit. For example, the improvement...
9042190 Apparatuses, sense circuits, and methods for compensating for a wordline voltage increase  
Apparatuses, sense circuits, and methods for compensating for a voltage increase on a wordline in a memory is described. An example apparatus includes a bitline, a memory cell coupled to the...
9042148 Content addressable memory  
An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a...
9036429 Nonvolatile memory device and operating method thereof  
A nonvolatile memory device including a memory cell arranged at a region where a word line and a bit line cross each other; a control signal generator configured to be enabled while the...
9036442 Reduced-noise reference voltage platform for a voltage converter device  
An electronic system, a reduced-noise reference voltage platform for a voltage converter device, and a method of manufacture of a reduced-noise reference voltage platform for a voltage converter...
9030890 Semiconductor memory apparatus  
A semiconductor memory apparatus includes a sense amplifier driving control unit configured to be applied with first and second driving voltages, and generate first to third sense amplifier...
9030900 Semiconductor device, semiconductor memory device and operation method thereof  
A semiconductor memory device includes a bit line sense amplification unit configured to sense/amplify data loaded on a bit line, and a driving control unit configured to supply a power line of...
9030863 Read/write assist for memories  
An integrated circuit includes one or more bit cells, a word line coupled to the one or more bit cells, and a dummy word line arranged with the word line to have a capacitance therebetween. The...
9025394 Memory devices and control methods thereof  
A memory device is provided. The memory device includes a first signal line, a memory cell array, first and second voltage adjustment circuits. The memory cell array is divided into first and...
9025401 Semiconductor memory device including bulk voltage generation circuit  
A semiconductor memory device includes a bulk voltage generation circuit configured to interrupt driving of a bulk voltage in response to an exit signal which is generated in synchronization with...
9025395 Data transmission circuit  
A data transmission circuit includes: a driving voltage generation unit configured to generate a driving voltage having a lower level than an external driving voltage; a switch unit configured to...
9025391 Circuit arrangement and method for operating a circuit arrangement  
A circuit arrangement, having a plurality of electronic components; a plurality of first access lines and second access lines, wherein each electronic component is coupled with at least one first...
9025403 Dynamic cascode-managed high-voltage word-line driver circuit  
A high-voltage word-line driver circuit for a memory device uses cascode devices to prevent any single transistor of the driver circuit from having the full power supply voltage from which the...
9025393 Method of optimizing solid state drive soft retry voltages  
A method of optimizing solid state drive (SSD) soft retry voltages comprises limiting a number of voltage reads and properly spacing and determining the reference voltage at which each voltage is...
9019781 Internal voltage generation circuit  
An internal voltage generation circuit includes: a selection unit configured to select one of first and second reference voltages as a selection reference voltage in response to a self refresh...
9019782 Dual rail memory architecture  
A memory macro comprises a plurality of memory cells, a plurality of first amplifying circuits, a first driver circuit, and a first level shifter. The plurality of memory cells is arranged in...
9013925 Nonvolatile semiconductor memory device  
A nonvolatile semiconductor memory device comprises a memory cell array, a staircase voltage generator, and a decode and level shift circuit. The memory cell array comprises a plurality of memory...
9013932 Semiconductor devices and semiconductor systems including the same  
A semiconductor system includes a controller and a semiconductor device. The controller outputs offset signals whose level combination is controlled according to temperature code signals including...
9013927 Sector-based regulation of program voltages for non-volatile memory (NVM) systems  
Methods and systems are disclosed for sector-based regulation of program voltages for non-volatile memory (NVM) systems. The disclosed embodiments regulate program voltages for NVM cells based...
9013942 Sense amplifier having loop gain control  
Memories, sense amplifiers, and methods for amplifying a current input are disclosed, including a sense amplifier including a bias circuit configured to provide a bias voltage having a magnitude...
9007867 Loading trim address and trim data pairs  
Methods of loading trim address and trim data pairs to a trim register array, and apparatus configured to perform such methods. The methods maintain a correspondence between the trim address and...
9007864 Information processing apparatus, nonvolatile storage device, information porcessing system and nonvolatile memory controller  
A host device includes a voltage source which is connected to a voltage line via a host voltage switch and which supplies a first voltage to the voltage line, a host regulator which is connected...
9007808 Safeguarding data through an SMT process  
Structures and methods for recovering data in a semiconductor memory device are disclosed herein. In one embodiment, a method of recovering data in a semiconductor memory device, can include: (i)...
9007854 Method and system for optimized soft decoding in a data storage device  
Systems and methods are disclosed for decoding solid-state memory cells. In certain embodiments, a data storage device includes a controller configured to decode a non-volatile memory array by...
9007845 Non-volatile semiconductor memory device  
In performing a read operation of a memory transistor, a control circuit supplies a first voltage to a selected word line connected to a selected memory transistor. A second voltage is supplied to...
9001596 Nonvolatile memory apparatus including sharing driver capable of performing both of read and write operation  
A nonvolatile memory apparatus includes a read/write control unit and a voltage generation unit and the memory cell. The read/write control circuit is configured to supply a bias voltage in...
9001610 Semiconductor device generating internal voltage  
Such a device is disclosed that includes an internal voltage generating circuit generating an internal voltage by lowering an external potential and supplying the generated internal voltage to a...
9001557 Variable resistance nonvolatile memory element writing method and variable resistance nonvolatile memory device  
Provided is a method of writing to a variable resistance nonvolatile memory element which is capable of both improving retention characteristics and enlarging a window of operation. In the method...
9001556 Semiconductor memory device and operation method thereof  
A semiconductor memory device according to an embodiment includes a control circuit configured to apply a first voltage to a selected first line, apply a second voltage to a selected second line,...
8996838 Structure variation detection for a memory having a three-dimensional memory configuration  
A data storage device includes a memory having a three-dimensional (3D) memory configuration. The memory includes a structure that extends through multiple layers of the memory. A method includes...
8995208 Static random access memory devices having read and write assist circuits therein that improve read and write reliability  
Integrated circuit memory devices include a memory cell configured to receive a power supply signal and a write assist circuit. The write assist circuit is configured to improve write margins by...
8995215 Semiconductor device and control method of the same  
The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit connected to a core cell provided...
8995204 Circuit devices and methods having adjustable transistor body bias  
Circuits, integrated circuits devices, and methods are disclosed that may include biasable transistors with screening regions positioned below a gate and separated from the gate by a semiconductor...
8988940 Structure and method for narrowing voltage threshold distribution in non-volatile memories  
Embodiments of the present invention provide a memory array of macro cells. Each macro cell comprises a storage element and a calibration element. The storage element and its corresponding...
8982608 Semiconductor device and data processing system  
A semiconductor device having a memory cell including a capacitor and a select transistor with a floating body structure, a bit line connected to the select transistor, a bit line control circuit,...
8976606 Voltage generating circuit and semiconductor device including the voltage generating circuit  
A voltage generating circuit includes first and second step-up circuits, each having first and second input terminals and an output terminal and configured to increase a voltage level of an input...
8976613 Differential current sensing scheme for magnetic random access memory  
A circuit for a differential current sensing scheme includes first and second cell segments, first and second reference cells, and first and second current sense amplifiers. The first and second...
8971123 Memory system temperature calibration  
A nonvolatile memory system includes a memory controller chip with at least one temperature sensor that is individually calibrated, at a single temperature, after the nonvolatile memory system is...
8971117 Apparatus and methods for applying a non-zero voltage differential across a memory cell not involved in an access operation  
Apparatus and methods for applying a non-zero voltage differential across a memory cell not involved in an access operation can facilitate improved data retention characteristics.
8971095 Memory architecture  
A write circuit in a memory array includes a global data line, a switching circuit, and a first local data line coupled with the switching circuit and with a first plurality of memory cells. The...
8971142 Semiconductor memory device and method of operating the same  
A semiconductor memory device includes a bit line pre-sense amplifier configured to sense a potential difference between bit line pair and amplify the voltages of the bit line pair based on the...
8964488 Non-volatile memory device using variable resistance element with an improved write performance  
A non-volatile memory device using a variable resistive element is provided. The non-volatile memory device includes a memory cell array having a plurality of non-volatile memory cells, a first...
8964489 Semiconductor memory device capable of optimizing an operation time of a boosting circuit during a writing period  
When writing into an antifuse memory element finishes, a value of resistance of the memory element rapidly decreases; accordingly, an output voltage of a boosting circuit which produces a writing...
8958263 Semiconductor device  
An object is to increase the retention characteristics of a memory device formed using a wide bandgap semiconductor. A bit line controlling transistor is inserted in a bit line in series. The...
8958251 Nonvolatile memory device and method of improving a program efficiency thereof  
A nonvolatile memory device includes a memory cell array including a plurality of memory cells, a page buffer circuit connected with the memory cell array via a plurality of bit lines and...
8958250 Method and apparatus for optimizing reference voltages in a nonvolatile memory  
A system including a divider module, a read module, a counting module, and a reference voltage setting module. The divider module is configured to select a voltage range in which to adjust a...
8953355 Memory dies, stacked memories, memory devices and methods  
Memory die, stacks of memory dies, memory devices and methods, such as those to construct and operate such die, stacks and/or memory devices are provided. One such memory die includes an...
8953383 Operating circuit controlling device, semiconductor memory device and method of operating the same  
A semiconductor memory device is kept in a busy state by controlling a ready/busy pad when a detection signal is output since an external voltage is less than a reference voltage, prevents...
8953387 Apparatuses and methods for efficient write in a cross-point array  
A memory circuit, including a memory array (such as a cross-point array), may include circuit elements that may function both as selection elements/drivers and de-selection elements/drivers. A...