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7313042 Thin film magnetic memory device having an improved read operation margin  
A data bus is precharged to a precharge voltage before data read operation. In the data read operation, the data bus thus precharged is electrically coupled to the same voltage as the precharge...
7313038 Nonvolatile memory including a verify circuit  
A semiconductor device includes a first nonvolatile memory element group which includes a plurality of first nonvolatile memory elements programmed with data by electrically and irreversibly...
7313037 RFID system including a memory for correcting a fail cell and method for correcting a fail cell using the same  
A radio frequency identification (RFID) system and a method for correcting a failed cell using the same are provided. The RFID system effectively corrects randomly distributed cell data by using a...
7313030 Differential flash memory programming technique  
The invention relates flash memory programming techniques. An object of the invention is to provide a flash memory programming technique avoiding problems of the known state of the art and in...
7310271 Program-verify method of non-volatile memory device  
A method for programming a non-volatile memory device includes applying a first program-verify voltage to a first word line to determine whether or not memory cells associated with the first word...
7310263 ROM storing information by using pair of memory cells  
Disclosed is a semiconductor device including a memory cell array, word lines, bit lines, and a signal difference determination circuit. In the memory cell array, memory cells each formed by...
7307911 Apparatus and method for improving sensing margin of electrically programmable fuses  
An apparatus for sensing the state of a programmable resistive memory element device includes a latch device is coupled to a fuse node and a reference node, the fuse node included within a fuse leg...
7307895 Self test for the phase angle of the data read clock signal DQS  
The invention relates to a semiconductor memory apparatus having at least one clock input contact for inputting an external clock signal, at least one clock output contact for outputting a data...
7307861 Content addressable memory (CAM) cell bit line architecture  
A ternary content addressable memory (TCAM) cell ( 100 ) can include two memory elements ( 102 - 0 and 102 - 1 ) with a single bit line ( 106 - 0 and 106 - 1 ) per memory element. A TCAM cell (...
7304886 Writing driver circuit of phase-change memory  
A writing driver circuit of a phase-change memory array which has a pulse selection circuit, a current control circuit, and a current drive circuit. The current control circuit receives a bias...
7304881 Ferroelectric memory with wide operating voltage and multi-bit storage per cell  
Apparatus and methods are described for a multi-level FeRAM memory device. Using write and read circuits associated with the memory device, multiple data states may be written to and read from the...
7304879 Non-volatile memory element capable of storing irreversible complementary data  
A non-volatile memory element for storing at least one data item, having a readable memory cell which can be written on with a first part of a data item, the memory cell exhibiting a first...
7304876 Compare circuit for a content addressable memory cell  
A ternary content addressable memory (CAM) cell is disclosed for providing reduced or minimized matchline (ML) capacitance and for increasing current between matchline and tail-line in the case of...
7304873 Method for on-the-fly error correction in a content addressable memory (CAM) and device therefor  
A CAM system ( 200 ) can include a number of entries ( 202 - 0 to 202 - 3 ) having one portion for storing a data value (e.g., E 1 ) and another portion for storing a replicated data value (E 1...
7301850 Content addressable memory (CAM) devices having bidirectional interface circuits therein that support passing word line and match signals on global word lines  
Content addressable memory devices include a bidirectional interface circuit configured to receive word line signals from a plurality of global word lines and pass match information from a selected...
7301844 Semiconductor device  
In a semiconductor device, an internally-generated power supply voltage VPP is monitored. If the internally-generated power supply voltage VPP is lower than a lower limit voltage, serial refresh is...
7301840 Semiconductor memory device  
There provided a semiconductor memory device which ensures writing to all memory cells regardless of fluctuations in properties of the memory cells caused by manufacturing error or the like and can...
7301839 Read operation for non-volatile storage that includes compensation for coupling  
Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge...
7301837 Error test for an address decoder of a non-volatile memory  
A non-volatile memory includes word lines providing access to memory cells, a word-line decoder applying an activation signal corresponding to an input address to a word line, a converter...
7301825 Method of controlling copy-back operation of flash memory device including multi-level cells  
A method of controlling a copy-back operation of a flash memory device including multi-level cells. In the method, the copy-back operation can be executed even without an additional storage space....
7301813 Compensating for coupling during read operations of non-volatile memory  
Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge...
7301808 Read operation for non-volatile storage that includes compensation for coupling  
Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge...
7298658 Semiconductor memory device using row redundancy and I/O redundancy scheme based on a preset order and a defect order  
To reduce the area relating to location of redundant elements for relieving defects of a memory. A memory device has row address and input/output data as two dimensional redundancy parameters for...
7298642 Magnetic resistance memory and method of writing data  
A magnetic resistance memory includes an identity determining unit that compares, bit by bit, first data stored in an address specified by a write request with second data to be written to the...
7298637 Multiple match detection circuit and method  
A multiple matchline sense circuit for detecting a single, more than one, or no match conditions during a search-and-compare operation of a content addressable memory is disclosed. The circuit...
7298636 Packet processors having multi-functional range match cells therein  
A multi-functional match cell is responsive to first and second n-bit operands and configured so that the match cell operates as an n-bit range match cell when the first and second n-bit operands...
7298635 Content addressable memory (CAM) cell with single ended write multiplexing  
A content addressable memory (CAM) cell circuit can include a match section that enables an impedance path coupled to a match line in response to a comparison between a data value and a compare...
7295478 Selective application of program inhibit schemes in non-volatile memory  
A non-volatile memory system is programmed so as to reduce or avoid program disturb. In accordance with one embodiment, multiple program inhibit schemes are employed for a single non-volatile...
7295473 System for reducing read disturb for non-volatile storage  
A system for reducing or removing a form of read disturb in a non-volatile storage device. One embodiment seeks to prevent read disturb by eliminating or minimizing boosting of the channel of the...
7295456 Chain ferroelectric random access memory (CFRAM) having an intrinsic transistor connected in parallel with a ferroelectric capacitor  
A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of...
7292491 Method and apparatus for controlling refresh operations in a dynamic memory device  
A method and apparatus are provided for controlling refresh operations of a dynamic memory device. The temperature of the dynamic memory device is detected. The detected temperature is then used to...
7292484 Sense amplifier with multiple bits sharing a common reference  
A memory circuit includes a sense amplifier in which a single reference signal is compared to two data signals from two memory cells. The reference signal is generated from the combination of...
7292483 Back-bias voltage generator for decreasing a current consumption of a self-refresh operation  
An internal voltage generator for generating a back bias voltage includes a back bias voltage pumping block for comparing a reference voltage with a feedback back bias voltage to generate a back...
7292471 Semiconductor memory device having a voltage-controlled-oscillator-based readout circuit  
By first readout, the current input from a selected cell is converted by a preamplifier and a VCO into pulses of a frequency inversely proportionate to the current value, and the number of the...
7290117 Memory having increased data-transfer speed and related systems and methods  
A memory includes an address bus, address counter, address decoder, comparator, and control circuit. During a data read or write cycle, the address bus receives an external address, the address...
7289371 Semiconductor memory device and electronic equipment  
A semiconductor memory device has a memory cell array in which a plurality of nonvolatile memory cells are arranged. The memory device also has word lines, bit lines connected with the memory cells...
7289364 Programmable memory device with an improved redundancy structure  
An electrically programmable memory device is proposed including: a matrix of memory cells arranged in a plurality of memory arrays and at least one redundancy array; and a substituting structure...
7289360 Multi-state memory  
Maximized multi-state compaction and more tolerance in memory state behavior is achieved through a flexible, self-consistent and self-adapting mode of detection, covering a wide dynamic range. For...
7286432 Temperature update masking to ensure correct measurement of temperature when references become unstable  
Embodiments of the invention generally provide methods and apparatuses for updating a temperature measurement. In one embodiment, the temperature measurement is performed by a temperature sensor...
7286429 High speed sensing amplifier for an MRAM cell  
A method and circuits are disclosed for sensing an output of a memory cell having high and low resistance states. A high reference cell is in high resistance state and a low reference cell is in...
7286419 Semiconductor memory device outputting identifying and roll call information  
A semiconductor memory device has an information storing circuit such as a fuse box as well as a memory cell array with redundant memory cells that can be used to replace defective memory cells....
7286412 Method and apparatus to improve nonvolatile memory data retention  
Disclosed are apparatuses, methods, and manufacturing methods relating to improving data retention in nonvolatile memory. In many embodiments, monitor reference currents in addition to a normal...
7286381 Non-volatile and-type content addressable memory  
In order to speed up the search for a data item in a content addressable memory and to simplify the circuit structure of the memory having associated with each row of cells a ground control line, a...
7286379 Content addressable memory (CAM) architecture and method of operating the same  
An improved Content Addressable Memory (CAM) architecture and method for operating the same is provided herein. The improved CAM architecture may generally include an array of memory cells arranged...
7283414 Method for improving the precision of a temperature-sensor circuit  
The preferred embodiments described below provide a method and memory device for improving the precision of a temperature-sensor circuit. In one preferred embodiment, first and second...
7283380 Content addressable memory with selective error logging  
A content addressable memory (CAM) device with selective error logging. The CAM device includes a CAM array and an error detection circuit coupled to receive a data value from a selected storage...
7280420 Data compression read mode for memory testing  
Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data compression test mode. In the data...
7280412 Circuits and methods for data bus inversion in a semiconductor memory  
A data bus inversion (DBI) circuit includes at least one DBI block configured to invert an input data signal based on the logic state of input data bits. The DBI block includes a comparison...
7280386 Method and system for controlling refresh to avoid memory cell data losses  
A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset...
7278004 Burst write in a non-volatile memory device  
A synchronous flash memory has been described that includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The synchronous...
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