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7106642 Semiconductor integrated circuit device in which a measure to counter soft errors is taken  
A semiconductor integrated circuit device includes a first memory circuit which stores normal data, a second memory circuit which stores determination information used to determine whether a value...
7106632 Integrated circuit with analog or multilevel storage cells and user-selectable sampling frequency  
Techniques are used to store information in a medium such as the memory cells of an integrated circuit, and also retrieval of information from the medium. The integrated circuit includes...
7102922 Thin film magnetic memory device capable of conducting stable data read and write operations  
A tunnel magnetic resistive element forming a magnetic memory cell includes a fixed magnetic layer having a fixed magnetic field of a fixed direction, a free magnetic layer magnetized by an applied...
7102911 Method for improving the read signal in a memory having passive memory elements  
A method for improving read signals in a memory including passive memory elements provided at crossover locations of word and bit lines, and in which stored digital information is represented by a...
7099232 Delay locked loop device  
An apparatus for detecting locking information of a DLL clock in a semiconductor memory device includes a delayed locked loop for generating a first comparison signal and a first delay end signal;...
7099188 Bit line reference circuits for binary and multiple-bit-per-cell memories  
Auto-tracking bit line reference schemes have common reference and normal word lines and generate a “½ cell current” reference by providing reference bit lines with pull-up devices having a...
7099171 Content addressable memory cell techniques  
A content addressable memory cell ( 10 ) includes a circuit ( 20 ) operating from a predetermined supply voltage (VDD) for storing a first bit of data at a first point ( 35 ) and a second bit of...
7095667 Noise resistant small signal sensing circuit for a memory device  
Apparatus and method for data sensing circuitry that uses averaging to sense small differences in signal levels representing data states. The apparatus periodically switches the coupling of input...
7095659 Variable voltage supply bias and methods for negative differential resistance (NDR) based memory device  
Static random access memory (SRAM) performance is enhanced through the use of appropriate latch strength control. For example, latch strength in an SRAM cell is increased during data store...
7095641 Content addressable memory (CAM) devices having priority class detectors therein that perform local encoding of match line signals  
Content addressable memory devices may include a priority encoder therein and a first tier of CAM arrays arranged side-by-side relative to each other, on a first side of the priority encoder. A...
7092308 Portable data storage apparatus  
A memory card including a non-volatile memory and a power management unit for receiving an external supply voltage to supply an operating voltage to the non-volatile memory, wherein when the...
7092271 CAM memory architecture and a method of forming and operating a device according to a CAM memory architecture  
A method for operating a content addressable memory that includes receiving a first data value for evaluation at a first memory block during a first time interval, receiving a second data value for...
RE39227 Content addressable memory (CAM) arrays and cells having low power requirements  
A content addressable memory (CAM) cell that includes a static random access memory (SRAM) cell that operates in response to a V CC supply voltage. A first set of bit lines coupled to the SRAM...
7088615 Multi-state memory  
Maximized multi-state compaction and more tolerance in memory state behavior is achieved through a flexible, self-consistent and self-adapting mode of detection, covering a wide dynamic range. For...
7088603 DRAM CAM memory  
A CAM device combines a folded bit line architecture with a standard six transistor DRAM based CAM cell and includes a sensing scheme where the active and reference bit lines being sensed are each...
7085180 Method and structure for enabling a redundancy allocation during a multi-bank operation  
A method for allocating redundancies during a multi-bank operation in a memory device which includes two or more redundancy domains is described. The method includes steps of enabling a pass/fail...
7085167 Methods for programming user data and confirmation information in nonvolatile memory devices  
Method of programming nonvolatile memory devices are provided in which data is programmed into a first plurality of memory cells of the nonvolatile memory device. At the same time associated...
7085147 Systems and methods for preventing malfunction of content addressable memory resulting from concurrent write and lookup operations  
Systems and methods for preventing the corruption of a CAM lookup result when a lookup in the CAM and a write to the CAM are concurrently executed. In one embodiment, a tag value is clocked into a...
7082070 Temperature detection circuit and temperature detection method  
A temperature detection circuit and method are provided. The temperature detection circuit samples a first delay time for an input signal at a target temperature to be detected, stores a first...
7082062 Voltage output control apparatus and method  
When the output of a boosted voltage is started by a boosted voltage generation circuit, the voltage supplied to memory cells and level shift circuits side through a current mirror circuit is...
7079409 Apparatus and method for power savings in high-performance CAM structures  
This invention reduces power consumed during CAM search operations in a CAM/RAM structure utilizing a segmented match line structure. This device is useful when it is known that a portion or...
7079407 Content addressable memory (CAM) device including match line sensing  
A content addressable memory (CAM) device that includes a plurality of CAM cells coupled to a match line to affect a voltage of the match line in response to data values of the CAM cells and...
7075849 Semiconductor memory device and layout method thereof  
Embodiments of the invention provide drivers from active internal voltage generating circuits on both sides of the internal voltage generating lines, therefore a voltage level of the internal...
7075822 High bandwidth datapath load and test of multi-level memory cells  
An apparatus and technique for testing of multi-level cells (MLC) in a memory storage device using a high bandwidth data path architecture. The technique includes hardware for obtaining a first...
7073047 Control chip and method for accelerating memory access  
A control chip and operating method for accelerating memory access that can be applied to a memory system whose memory read command actual address is read from a system bus in a number of...
7072239 Method and circuit for locating anomalous memory cells  
A method for locating in an array of memory cells a set of cells having a stand-by current that exceeds a certain value based on their programming state. The method includes selecting all the cells...
7072238 Semiconductor device capable of generating ripple-free voltage internally  
A semiconductor device that generates a regulated high voltage. The device includes, a high voltage generation circuit for supplying a high voltage to the first power line, a current bypass circuit...
7072229 Memory system having fast and slow data reading mechanisms  
There is provided a memory for storing data comprising: a fast data reading mechanism operable to read a data value from said memory to generate a fast read result that is output from said...
7068566 Semiconductor memory device capable of outputting data when a read request not accompanied with an address change being issued  
The present invention provides a technique of causing a semiconductor device to output data if a read request not accompanied with an address change is issued. In a first situation in which a write...
7068565 Clock control in sequential circuit for low-power operation and circuit conversion to low-power sequential circuit  
Clock control of a sequential circuit is realized with the assumptions that stop of a clock is impossible due to the specifications, and feedback of the output of a memory element does not exist....
7068554 Apparatus and method for implementing multiple memory redundancy with delay tracking clock  
A memory redundancy control apparatus includes a static compare stage configured to compare bits of a requested memory address to corresponding fuse information bits representing a defective memory...
7064987 Memory address generator with scheduled write and read address generating capability  
A memory address generator includes a write address generator for generating write addresses to be used in writing of data units of an input data block into a memory device in a non-raster scan...
7061825 Semiconductor integrated circuit  
A semiconductor integrated circuit includes a memory circuit, an oscillator circuit which generates an internal clock signal, based on control information held in the memory circuit, and a logic...
7061789 Sensing scheme for programmable resistance memory using voltage coefficient characteristics  
A method and apparatus for sensing the resistance state of data in a resistance memory cell by using the voltage coefficient of the cell instead of only its resistance. A voltage potential is...
7061782 Content addressable memory (CAM) for data lookups in a data processing system  
Power consumption is reduced in a content addressable memory of a data processing system or a data processor. The content addressable memory includes at least a first single bit storage ( 101; 301...
7057969 Self-timed sneak current cancellation  
A sensing circuit. The circuit includes an integrator to sense charge release from a passive electronic device and a comparator to interpret the charge release as one of at least two data states....
7057958 Method and system for temperature compensation for memory cells with temperature-dependent behavior  
The preferred embodiments described herein relate to a method and system for temperature compensation for memory cells with temperature-dependent behavior. In one preferred embodiment, at least one...
7057948 Semiconductor integrated circuit device having a test function  
A semiconductor memory device includes a memory collar, a repair data analyzer, a BIST block, and a system logic. The memory collar includes a memory cell and a spare cell and have a redundancy...
7057944 Semiconductor readout circuit  
A semiconductor readout circuit reads out a potential of each of plural data lines by comparing the potential with a potential of a common reference data line, using a sense amplifier provided for...
7057917 Ferroelectric memory with an intrinsic access transistor coupled to a capacitor  
A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of...
7057913 Low-power search line circuit encoding technique for content addressable memories  
A circuit for searching a content addressable memory includes a driver which generates a plurality of search line values, different combinations of which are used to implement a one-hot encoding...
7057912 Semiconductor device  
A T-CAM array is provided made up of ternary dynamic CAM cells each including a plurality of transistors. A refresh operation can be performed while reading out stored data to a match line using...
7054209 Semiconductor memory device and test method thereof  
A semiconductor memory device vice disclosed herein comprises: a memory cell array divided into a plurality of blocks, each of which includes a plurality of memory cells; a plurality of row...
7054204 Semiconductor device and method for controlling the same  
Disclosed herein are a semiconductor method and device which are capable of reducing data write errors by rewriting last write data during a write recovery time (tWR). The semiconductor device...
7054183 Adaptive programming technique for a re-writable conductive memory device  
A programming circuit is provided. As a conductive memory cell is programmed, its resistance changes. The provided programming circuit monitors the changing resistance while programming the memory...
7051178 Burst write in a non-volatile memory device  
A synchronous flash memory has been described that includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The synchronous...
7051004 System and methods providing secure delivery of licenses and content  
A computer network having a requesting node and a providing node permits data transfer therebetween when permitted by an authorizing node. Reports generated in response to authorizations and...
7050349 Semiconductor integrated circuit device and semiconductor memory device reprogrammable after assembly  
A programming circuit includes an LT fuse read circuit programming a defective address during a wafer-processing, an electrical fuse circuit electrically programming a defective address, an...
7050318 Selective match line pre-charging in a CAM device using pre-compare operations  
A CAM device for comparing a search key with a plurality of CAM words stored in a main CAM array includes a pre-compare CAM array and match line control logic. The pre-compare CAM array includes a...
7046568 Memory sensing circuit and method for low voltage operation  
A sensing module operates with a sense amplifier sensing a conduction current of a memory cell via a coupled bit line under constant voltage condition in order to minimize bit-line to bit-line...
Matches 201 - 250 out of 1850 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >