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7391657 |
Semiconductor memory chip
A semiconductor memory chip includes: a reception interface section for receiving external data, command, and address signals in form of serial signal frames; an intermediate data buffer for...
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7391656 |
Self-feedback control pipeline architecture for memory read path applications
A memory reading apparatus transfers digital data from a memory array that is independent of external clocking rate, where the data transmission time is not limited by the external clock period,...
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7391649 |
Page buffer and non-volatile memory device including the same
In one aspect, a non-volatile memory device includes a non-volatile memory cell array and a page buffer. The page buffer includes a sense node selectively connected to a bit line of the memory cell...
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7388794 |
Individual I/O modulation in memory devices
A DRAM circuit with reduced power consumption and in some circumstances faster memory array access speed. Input/output lines connected to a memory array are sensed according to their...
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7388793 |
Method for configuring a voltage regulator
A voltage regulator connected to a memory cell is configured by identifying at least a first and a second operation regions of the cell and associating the first and second operation regions with...
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7388772 |
Latch circuit
A latch circuit comprises eight MOS transistors in which a first pair of transistors are connected in series between a voltage supply node and ground and a second pair of transistors are connected...
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7386768 |
Memory channel with bit lane fail-over
Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory...
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7385872 |
Method and apparatus for increasing clock frequency and data rate for semiconductor devices
An embodiment of the present invention receives a data signal and at least one data shift signal that facilitates adjustment of the data signal and produces a resulting data signal with a data rate...
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7385850 |
Method of programming and verifying cells of a nonvolatile memory and relative NAND FLASH memory
A method of programming cells in a nonvolatile memory is based upon a Global Verify operation and a Byte-by-byte Verify operation. The cells of a destination page of the nonvolatile memory are...
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7385847 |
Semiconductor device
A semiconductor device includes an electrical circuit formed on a substrate; a level detector outputting a first level signal which has a signal level based on power supply voltage and which...
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7385840 |
SRAM cell with independent static noise margin, trip voltage, and read current optimization
An SRAM memory cell structure utilizing a read driver transistor and a column select write transistor, and a method of operating the same. The SRAM memory cell comprises first and second...
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7382637 |
Block-writable content addressable memory device
A content addressable memory device including a memory to store a searchable database, a search circuit, and a first-in-first-out storage circuit. The search circuit generates a plurality of...
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7379383 |
Methods of DDR receiver read re-synchronization
A method for reading data is provided. The method includes generating two or more pulses from a first clock signal by which the data to be read is received, using each generated pulse to latch data...
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7379382 |
System and method for controlling timing of output signals
The timing of output signals can be controlled by coupling a digital signal through a signal distribution tree having a plurality of branches extending from an input node to respective clock inputs...
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7379350 |
Semiconductor memory device operating using read only memory data
A semiconductor memory device operating using initialization data, includes a first latch circuit which latches the initialization data, a memory cell array including a plurality of memory cells...
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7379341 |
Loading data with error detection in a power on sequence of flash memory device
A method of performing a power on sequence for a flash memory includes applying device voltage to the flash memory and loading nonvolatile memory data and nonvolatile memory complementary data to a...
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7379333 |
Page-buffer and non-volatile semiconductor memory including page buffer
In one aspect, a non-volatile memory device is provided which is operable in a programming mode and a read mode. The memory device includes a memory cell array which includes a plurality of...
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7376889 |
Memory device capable of detecting its failure
A memory device capable of detecting its failure, the memory device includes a data input section for receiving data applied from an external part of the memory device; a latch section for...
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7376871 |
CAM test structures and methods therefor
Configurations and methods that enable the testing of CAM-specific circuitry, even if the memory is defective, are implemented by utilizing various test modes. Accordingly, the CAM can be debugged...
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7376044 |
Burst read circuit in semiconductor memory device and burst data read method thereof
A semiconductor memory device conducts a burst read operation that avoids interrupt loading on a system. The memory device includes a memory cell array, a sense amplifier, a latch circuit and a...
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7376041 |
Semiconductor memory device and data read and write method of the same
A semiconductor memory device includes a memory cell array to store data; a data input portion to output data to the memory cell array in response to a write control signal; a data output portion...
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7376034 |
Parallel data storage system
A parallel data storage system for storing data received from, or retrieving data to, a host system using multiple data storage devices. The system includes an interface for communicating with the...
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7376029 |
Semiconductor memory devices including precharge circuit and methods for precharging
A precharge circuit of a semiconductor memory device may include a precharge controller, a first precharge unit and a second precharge unit. The precharge controller may enable a first control...
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7376022 |
Method using a one-time programmable memory cell
A one-time programmable device includes a controller, a protection system, a static storage element and a latch, which can be referred to as a latch-based one-time programmable (OTP) element. In...
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7376021 |
Data output circuit and method in DDR synchronous semiconductor device
Embodiments of the present invention include a data output circuit that can read data in parallel from a plurality of latches in a pipeline circuit. Even-numbered data and odd-numbered data are...
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7376020 |
Memory using a single-node data, address and control bus
An integrated circuit digital device is coupled to a memory with a single-node data, address and control bus. The memory may be a non-volatile memory and/or volatile memory. The memory may be...
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7372767 |
Nonvolatile semiconductor memory device having multi-level memory cells and page buffer used therefor
A non-volatile semiconductor memory device includes a memory array having nonvolatile memory cells. The memory device also includes a page buffer coupled to the memory array through first and...
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7372745 |
Semiconductor memory device with no latch error
A dynamic random access memory (DRAM) includes a data signal input circuit configured to input a data signal in response to a data control signal, and a data strobe signal input circuit configured...
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7372744 |
Memory system which copies successive pages, and data copy method therefor
A memory system includes a memory cell array, a bit line switch, first and second page buffers, a column switch, an error correction circuit, and control circuits. The second page buffer can swap...
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7372735 |
Non-volatile semiconductor memory device
A non-volatile semiconductor memory device includes a non-volatile memory element group having a first storage area which stores booting data and a second storage area to store storage addresses of...
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7370163 |
Adaptive cache engine for storage area network including systems and methods related thereto
Featured is a data storage back-up system for replication, mirroring and/or backing-up data including one or more first and second data storage devices that embody iSCSI, FC or alike principals and...
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7370140 |
Enhanced DRAM with embedded registers
An enhanced DRAM contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are...
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7369455 |
Calibration circuit of a semiconductor memory device and method of operating the same
A calibration circuit for a semiconductor device and a method of driving the same. The calibration circuit includes a PRBS generator in which a data pattern is generated within an integrated...
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7369452 |
Programmable cell
A device having an OTP memory is disclosed. A program state of the OTP device is stored at a fuse that is connected in series between a first node and a latch. During a program mode, the first node...
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7369451 |
Dynamic random access memory device and method for self-refreshing memory cells
A dynamic random access memory (DRAM) device having memory cells is operated in a self-refresh mode and a normal mode. A mode detector provides a self-refresh mode signal in the self-refresh mode...
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7369450 |
Nonvolatile memory having latching sense amplifier and method of operation
A memory comprises a sense amplifier for sensing a logic state of a selected bitline. The sense amplifier includes a first precharge circuit, a current-to-voltage converter, a latch circuit, and a...
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7369448 |
Input circuit for memory device
An input circuit for a semiconductor memory device is disclosed. The input circuit controlling transmission paths for data having passed through a data input buffer by using a 1-clock shifted block...
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7369447 |
Random cache read
A non-volatile memory is described that utilizes a cache read mode of operation, where a next page of memory is being read/sensed from the memory array by the sense amplifiers while a previously...
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7369446 |
Method and apparatus to prevent high voltage supply degradation for high-voltage latches of a non-volatile memory
An improved cross-coupled CMOS high-voltage latch that is used for storing data bits to be written to memory cells of a non-volatile memory is provided with a switching circuit that, during writing...
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7369437 |
System for reading non-volatile storage with efficient setup
A process for reading data (including verifying during programming) from a selected non-volatile storage elements of a group (e.g., NAND string) of non-volatile storage elements includes...
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7366827 |
Method and apparatus for selectively transmitting command signal and address signal
A method for transmitting a command signal and an address signal to a rank which is to be accessed includes receiving and buffering the command signal and the address signal, and transmitting the...
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7366821 |
High-speed memory system
A memory system has a memory controller and a plurality of memories. The plurality of memories are connected via a switch to an end of a bus, which is connected to the memory controller, wherein...
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7366820 |
Second-cache driving/controlling circuit, second cache, RAM, and second-cache driving/controlling method
A circuit for driving and controlling a second cache that is incorporated in a processor and comprises a plurality of RAM. The circuit comprises a second-cache control unit 1 A and a chip-enable...
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7366052 |
Memory device, memory system and method of inputting/outputting data into/from the same
A memory device includes a memory cell array, a row decoding section, a K-bit prefetch section and an output buffer section. The row decoding section decodes a row address in response to a first...
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7366044 |
Systems and methods for data transfers between memory cells
Systems and methods for reducing the latency of data transfers between memory cells by enabling data to be transferred directly between sense amplifiers in the memory system. In one embodiment, a...
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7366041 |
Input buffer for low voltage operation
An input buffer having differential amplifiers for receiving input signals to generate an output signal. The input buffer operates with a relatively low supply voltage and a relatively wide range...
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7366037 |
Semiconductor memory
A semiconductor memory includes: first and second bit lines; a precharge circuit for precharging the first and second bit lines to a predetermined potential; a plurality of memory cells each...
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7366033 |
3-level non-volatile semiconductor memory device and method of driving the same
A page buffer for a non-volatile semiconductor memory device includes a switch configured to couple a first bitline coupled to a first memory cell to a second bitline coupled to a second memory...
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7366032 |
Multi-ported register cell with randomly accessible history
A multi-ported register cell. The register cell includes a base cell and a plurality of history cells, each of which is coupled to the base cell. Each of the plurality history cells is coupled to...
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7363442 |
Separate handling of read and write of read-modify-write
A method, an apparatus, and a computer program are provided for the separate handling of read and write operations of Read-Modify-Write Commands in an XDR™ memory system. This invention allows...
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