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9041436 Semiconductor device having pull-up circuit and pull-down circuit  
To reduce power supply noises occurring in a control circuit unit for controlling an output buffer. A semiconductor device includes unit buffers for driving a data output terminal, impedance...
9042160 Memory device with resistive random access memory (ReRAM)  
A method includes, in a data storage device that includes a non-volatile memory and a resistive random access memory (ReRAM) on the same die, receiving data from a memory controller via a bus. The...
9042177 Semiconductor device and method of operating the same  
A semiconductor device includes first memory blocks arranged in a longitudinal direction, and including a plurality of strings, wherein the strings are formed along a vertical direction, and the...
9036412 Memory device and method of determining read voltage of memory device  
A method of operating a memory device includes applying an initial read voltage to a selected wordline to perform a read operation on memory cells connected to the selected wordline, determining...
9036446 Global reset with replica for pulse latch pre-decoders  
A global reset generation method for a pulse latch based pre-decoders in memories that comprises generating a pre-decoded memory address output for a pulse latch circuit, generating a reset signal...
9036441 Anti-fuse circuit in which anti-fuse cell data is monitored, and semiconductor device including the same  
An anti-fuse circuit in which anti-fuse program data may be monitored outside of the anti-fuse circuit and a semiconductor device including the anti-fuse circuit are disclosed. The anti-fuse...
9036433 Data transfer circuit and memory including the same  
A data transfer circuit includes a plurality of first lines, a second line suitable for receiving data from a first line selected among the first lines, a third line suitable for transferring data...
9030875 Non-volatile memory device  
A non-volatile memory device includes a memory cell array in which a plurality of bit lines intersect a plurality of word lines and a non-volatile memory cell is disposed at each intersection, a...
9030889 Buffering systems for accessing multiple layers of memory in integrated circuits  
Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of...
9030888 Semiconductor device having output buffer circuit in which impedance thereof can be controlled  
A device that includes first and second buffer circuits electrically connected to a terminal and an output control circuit activating the first buffer circuit and deactivating the second buffer...
9025397 Data write circuit of semiconductor apparatus  
A data write circuit of a semiconductor apparatus includes a data path configured to receive a pattern signal and generate a first delayed pattern signal; a data strobe signal path configured to...
9025384 Memory system and operating method of controller  
A memory system including a first memory of a first type; a second memory of a second type; and a controller configured to control the first memory and the second memory. The first type and second...
9025400 Semiconductor storage device  
A semiconductor storage device according to the present embodiment includes a plurality of memory units respectively comprising a plurality of memory cells. A data bus is shared by the memory...
9025395 Data transmission circuit  
A data transmission circuit includes: a driving voltage generation unit configured to generate a driving voltage having a lower level than an external driving voltage; a switch unit configured to...
9025403 Dynamic cascode-managed high-voltage word-line driver circuit  
A high-voltage word-line driver circuit for a memory device uses cascode devices to prevent any single transistor of the driver circuit from having the full power supply voltage from which the...
9019779 Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules  
A layout for simultaneously sub-accessible memory modules is disclosed. In one embodiment, a memory module includes a printed circuit board having a plurality of sectors, each sector being...
9018975 Methods and systems to stress-program an integrated circuit  
Methods and systems to stress-program a first integrated circuit (IC) block to output a pre-determined value upon activation/reset, such as to support time-zero compensation/trimming. To program,...
9019780 Non-volatile memory apparatus and data verification method thereof  
A non-volatile memory apparatus and a data verification method thereof are provided. The non-volatile memory apparatus includes a plurality of memory cells, a page buffer, a write circuit, a sense...
9019776 Memory access circuit for double data/single data rate applications  
A memory access circuit includes a write data circuit and a first write switch circuit. The write data circuit is used for receiving double data rate data or single data rate data, and outputting...
9019790 Apparatus and method for refreshing DRAM  
A refresh method for DRAM is provided, in which a memory cell array is arranged to have multiple storing pages. Each storing page has a counter value. The method includes detecting out a portion...
9013931 Semiconductor memory device and method for testing the same  
A semiconductor memory device includes a compression unit configured to compress a plurality of data, which are read from a memory cell region based on successive read commands and addresses, and...
9013921 Semiconductor memory device  
A semiconductor memory device includes a first data bus having a first width, and a second data bus which is separate from the first data bus and which has a second width which is different from...
9013950 Column select signal generation circuit  
A column select signal generation circuit includes: a first current controller configured to control the level of a pre-column select signal in response to a bank active signal, a driver...
9013934 Method of operating a nonvolatile memory by reprogramming failed cells using a reinforced program pulse in an idle state and memory system thereof  
A memory system, and an operation method of a nonvolatile memory, include programming memory cells using a normal program pulse, reading out a first set of data from the memory cells, detecting...
9013942 Sense amplifier having loop gain control  
Memories, sense amplifiers, and methods for amplifying a current input are disclosed, including a sense amplifier including a bias circuit configured to provide a bias voltage having a magnitude...
9007291 Active level shift driver circuit and liquid crystal display apparatus including the same  
An active level shift (ALS) driver circuit and a liquid crystal display apparatus including the ALS driver circuit are disclosed. The ALS driver circuit includes an input unit configured to apply...
9007851 Memory read techniques using Miller capacitance decoupling circuit  
Some embodiments relate to a sense amplifier output buffer configured to buffer an output of a sense amplifier. The sense amplifier output buffer includes a first pull-up element having a source...
9007849 Buffer control circuit of semiconductor memory apparatus  
A buffer control circuit of a semiconductor memory apparatus includes a delay unit configured to determine delay amounts for a command in response to a plurality of command latency signals, delay...
9007850 Page buffer, memory device comprising page buffer, and related method of operation  
A page buffer comprises a static latch configured to store data received from an external device, and a dynamic latch configured to receive the data stored in the static latch through a floating...
9007852 Semiconductor integrated circuit  
A semiconductor integrated circuit includes: a latch unit configured to latch data in response to an input control signal; and a latch control unit configured to determine whether or not any one...
9001595 Data strobe enable circuitry  
An integrated circuit may include memory interface circuitry that is used to communicate with off-chip memory. The memory interface circuitry may include data strobe (DQS) enable circuitry that...
9001576 Semiconductor memory device and method of operating the same  
A method of operating a semiconductor memory device includes checking an erase-program cycling number, setting a target erase level to be maintained when the erase-program cycling number is less...
9001611 Three-dimensional two port register file  
An integrated circuit that includes an array of memory cells. The integrated circuit also includes a write address row decoder having a plurality of write row outputs and a write address column...
9001594 Apparatuses and methods for adjusting a path delay of a command path  
Apparatuses and method for adjusting a path delay of a command path are disclosed. In an example apparatus, a command path configured to provide a command from an input to an output includes an...
8988953 Memories and methods for sharing a signal node for the receipt and provision of non-data signals  
Memories and methods for providing and receiving non-data signals at a signal node are disclosed. One such memory includes first and second signal nodes, and first and second signal buffer. The...
8988959 Circuit and method for dynamically changing a trip point in a sensing inverter  
A circuit and method for dynamically changing trip point voltage in a sensing inverter circuit. In one embodiment, the sensing inverter circuit includes: (1) a base inverter circuit couplable to...
8988101 Method for operating memory device and apparatuses performing the method  
According to example embodiments, a method for operating a memory device includes receiving an on-die termination (ODT) signal through an ODT pin, and issuing a command or controlling an ODT...
8988950 Data loading circuit and semiconductor memory device comprising same  
A data loading circuit comprises a non-volatile memory configured to store non-volatile data and output a serial data signal based on the stored non-volatile data in response to a power-up...
8988102 On-die termination  
Local on-die termination controllers for effecting termination of a high-speed signaling links simultaneously engage on-die termination structures within multiple integrated-circuit memory devices...
8982646 Semiconductor memory device including data transfer bus and data transfer method of the device  
According to one embodiment, a semiconductor memory device includes a memory cell array, a data bus, a transfer controller, column blocks, and a column selector. The data bus is divided into...
8982618 Nonvolatile memory device and related method of operation  
A nonvolatile memory device comprises a nonvolatile memory chip comprising a static latch, first and second dynamic latches that receive the data stored in the static latch through a floating...
8982650 Memory interface circuit and timing adjusting method  
A memory interface circuit, which controls capture timing of data provided from a memory according to a strobe signal provided from the memory, includes a control unit that controls an activation...
8982655 Apparatus and method for compression and decompression of microprocessor configuration data  
An apparatus is contemplated for storing and providing configuration data to a microprocessor. The apparatus has a core, disposed on a die, and a fuse array, disposed on the die and coupled to the...
8984320 Command paths, apparatuses and methods for providing a command to a data block  
Command paths, apparatuses, and methods for providing a command to a data block are described. In an example command path, a command receiver is configured to receive a command and a command...
8976607 High-speed memory write driver circuit with voltage level shifting features  
Various aspects of a fast, energy efficient write driver capable of efficient operation in a dual-voltage domain memory architecture are provided herein. Specifically, various aspects of the write...
8976604 Method and apparatus for copying data with a memory array having redundant memory  
A page copy operation such as copy back programming is performed between a source page of the memory array and a destination page of the memory array in different segments. The segments divide the...
8976618 Decoded 2N-bit bitcells in memory for storing decoded bits, and related systems and methods  
Decoded 2n-bit bitcells in memory for storing decoded bits, and related systems and methods are disclosed. In one embodiment, a decoded 2n-bit bitcell containing 2n state nodes is provided. Each...
8971116 Semiconductor device and method of operating the same  
A semiconductor device includes a plurality of page buffers coupled to bit lines and suitable for performing a verification operation to output a verification signal to a verification terminal,...
8971097 SRAM bit-line and write assist apparatus and method for lowering dynamic power and peak current, and a dual input level-shifter  
Described is an apparatus comprising a plurality of memory arrays, local write assist logic units, and read/write local column multiplexers coupled together in a group such that area occupied by...
8971146 Dual-port SRAM with bit line clamping  
In one embodiment, a memory includes a plurality of bit lines and a write driver for driving a driven bit line selected from the plurality of bit lines during a write operation. The write driver...