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7391664 |
Page mode access for non-volatile memory arrays
An array of non-volatiel memory cells arranged in logical columns and logical rows, and associated circuitry to enable reading or writing one or more memory cells on a row in parallel. In some...
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7391635 |
Method and apparatus for variable-resolution memory
An apparatus and method for storage and retrieval of memory content including a storage structure containing a plurality of memory elements addressable as a two-dimensional array of memory content...
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7388798 |
Semiconductor memory device including memory cell without capacitor
A semiconductor memory device including a memory cell without a capacitor includes: a memory cell array block including first memory cells connected between a first bit line and first word lines...
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7385859 |
Semiconductor memory devices and methods for generating column enable signals thereof
A semiconductor memory device includes a column enable signal generator, a row enable signal generator and a final column enable signal generator. The column signal enable generator may generate a...
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7385856 |
Non-volatile memory device and inspection method for non-volatile memory device
A non-volatile memory device comprises a plurality of bit lines extending in a first direction, a plurality of word lines extending in a second direction substantially perpendicular to the first...
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7382679 |
Semiconductor memory device
Disclosed is a semiconductor memory device which comprises an internal clock generating circuit receiving a clock signal from outside to generate an internal clock signal to be supplied to a random...
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7382673 |
Memory having parity generation circuit
A memory includes a column segment including memory cells along word lines, and a parity generation circuit configured to receive a first serial data stream of data bit values stored in memory...
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7382664 |
Simultaneous reading from and writing to different memory cells
A nonvolatile memory array includes a grid of word lines WL 1 , . . . ,WL 6 and bit lines BL 1 , . . . ,BL 8 . Of a plurality of memory cells 210 , each memory cell is located at an intersection...
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RE40356 |
Large-capacity semiconductor memory with improved layout for sub-amplifiers to increase operational speed
A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and...
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7380076 |
Information processing apparatus and method of accessing memory
The present invention makes it possible to inexpensively and quickly execute a process of rewriting data stored in a memory, thus reducing the power consumption of an information processing...
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7379349 |
Simultaneous and selective memory macro testing
A semiconductor device includes: a plurality of memory macros, each of which includes a plurality of memory cells, is activated in accordance with a corresponding active macro selection signal, and...
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7376021 |
Data output circuit and method in DDR synchronous semiconductor device
Embodiments of the present invention include a data output circuit that can read data in parallel from a plurality of latches in a pipeline circuit. Even-numbered data and odd-numbered data are...
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7376020 |
Memory using a single-node data, address and control bus
An integrated circuit digital device is coupled to a memory with a single-node data, address and control bus. The memory may be a non-volatile memory and/or volatile memory. The memory may be...
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7372755 |
On-chip storage memory for storing variable data bits
An improved on-chip storage memory and method for storing variable data bits, the memory including an on-chip storage memory system for storing variable data bits that has a memory for storing data...
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7372749 |
Methods for repairing and for operating a memory component
In a method for repairing a memory component, data retention times of regular memory cells are determined. Weak regular memory cells having a data retention time that is shorter than a...
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7372741 |
Nonvolatile memory apparatus having a processor and plural memories one or more of which is a nonvolatile memory having circuitry which performs an erase operation and an erase verify operation when the processor specifies the erase operation mode to the nonvolatile memory
A nonvolatile memory apparatus which includes plural memories one of which is a nonvolatile memory such as a Flash EEPROM capable of being specified a plurality of operations from a processing unit...
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7370140 |
Enhanced DRAM with embedded registers
An enhanced DRAM contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are...
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7369449 |
Semiconductor integrated circuit and data output method
A semiconductor integrated circuit for reducing power consumption and simultaneous switching noise in an output circuit, which outputs plural pieces of output data including first and second output...
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7369445 |
Methods of operating memory systems including memory devices set to different operating modes and related systems
A method of operating a memory system including a plurality of memory devices coupled to a command address bus may be provided. In particular, a first memory device of the plurality of memory...
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7369438 |
Combo memory design and technology for multiple-function java card, sim-card, bio-passport and bio-id card applications
A combination volatile and nonvolatile memory integrated circuit has at least one volatile memory array placed on the substrate and multiple nonvolatile memory arrays. The volatile and nonvolatile...
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7366032 |
Multi-ported register cell with randomly accessible history
A multi-ported register cell. The register cell includes a base cell and a plurality of history cells, each of which is coupled to the base cell. Each of the plurality history cells is coupled to...
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7366008 |
Radiation tolerant SRAM bit
In an integrated circuit, a radiation tolerant static random access memory device comprising a first inverter having an input and an output, a second inverter having an input and an output. A first...
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7362650 |
Memory arrangement having a plurality of RAM chips
Embodiments of the invention provide a memory arrangement having an even number k=4 of physically spaced RAM chips, on each of which it is possible for m data items to be simultaneously written or...
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7355895 |
Nonvolatile semiconductor memory and driving method the same
A nonvolatile semiconductor memory includes a memory cell array, a control circuit and an address control circuit. In the memory cell array, a plurality of memory cells are arranged in a matrix of...
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7353357 |
Apparatus and method for pipelined memory operations
A semiconductor memory device has a memory core that includes at least eight banks of dynamic random access storage cells and an internal data bus coupled to the memory core. The internal data bus...
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7349266 |
Memory device with a data hold latch
A memory device includes a plurality of pairs of complimentary bit lines and a plurality of latch circuits. Each pair of the plurality of pairs of complimentary bit lines is coupled to a column of...
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7345942 |
Memory circuit with automatic refresh function
According to the present invention, a memory circuit requiring refresh operations a first circuit which receives a command in synchronization with a clock signal, and which generates a first...
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7339825 |
Nonvolatile semiconductor memory with write global bit lines and read global bit lines
A nonvolatile semiconductor memory is capable of dual and triple operation with a small chip size. A plurality of sectors is formed. Each sector has nonvolatile memory cells, local bit lines...
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7333388 |
Multi-port memory cells
A memory array comprises memory cells of the dynamic type having a first and a second port. A cache memory is connected to the address and data paths of the first and second ports. A refresh...
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7333372 |
Reset circuit and integrated circuit device with reset function
A reset circuit, which generates a reset signal for initializing an internal circuit of an integrated circuit device having an auto-loading function, includes a first register which stores a...
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7330391 |
Memory having directed auto-refresh
A memory includes at least two memory banks, each memory bank including an array of memory cells including rows and columns. The memory includes a directed auto-refresh memory bank selection...
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7327612 |
Method and apparatus for providing the proper voltage to a memory
A method includes querying a memory to determine what type of voltage the memory requires and applying the proper operating voltage to the memory based on the query. An apparatus that supports...
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7317656 |
Semi-conductor memory component, and a process for operating a semi-conductor memory component
The invention relates to a semi-conductor memory component and process for operating a semi-conductor memory component, including activating the memory cells of a memory cell array, when one or...
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7315477 |
Compensating for coupling during read operations of non-volatile memory
Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge...
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7313031 |
Information processing apparatus and method, memory control device and method, recording medium, and program
A memory control device for writing to a memory data input via a port section and for reading from the memory data output via the port section includes setting means for setting, in accordance with...
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7310274 |
Semiconductor device
A semiconductor device includes a first memory block having a first address space, a second memory block having a second address space which is smaller than the first address space, and a test...
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7310260 |
High performance register accesses
The use of a bus clock is eliminated in communication between a cpu, or mpu, and a register block. The communication between the cpu/mpu and the register block is made combinatorial, such that the...
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7307893 |
Semiconductor device and method for controlling the same
A semiconductor memory device has a read ground and a write ground, these grounds being separately provided. Even when the read and verify operations are simultaneously executed, the source...
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7304896 |
Method and circuit for simultaneously programming memory cells
A method for simultaneously programming a pre-established number of memory cells includes setting an initial number of memory cells to be simultaneously programmed equal to the pre-established...
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7301795 |
Accelerated low power fatigue testing of FRAM
Systems and methods fatigue a ferroelectric memory device. Within a single cycle, a group of selected ferroelectric memory cells is fatigued by reading a first logical value from the cells while...
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7301794 |
Non-volatile memory array with simultaneous write and erase feature
A non-volatile transistor memory array has individual cells with a current injector and a non-volatile memory transistor. Injector current gives rise to charged particles that can be stored in the...
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7298640 |
1T1R resistive memory array with chained structure
A 1T1R resistive memory array comprised of chains of memory cells, where each memory cell is composed of a resistive element in parallel with a switch. Such chains of memory cells are non-volatile...
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7295481 |
Power saving by disabling cyclic bitline precharge
A method and system of accessing memory cells within a dynamic hardware memory block operated with a bitline precharge circuit, in which differential read/write access operations are performed by...
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7295477 |
Semiconductor memory device and method for writing data into the semiconductor memory device
A semiconductor memory device comprises a wordline ( 40 ), a first bitline ( 21 a ), two second bitlines ( 22 a , 22 b ), a first memory cell ( 100 a ) and a second memory cell ( 100 b ). The first...
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7289372 |
Dual-port memory array using shared write drivers and read sense amplifiers
Dual port memory blocks that have a reduced layout area are provided. The write drivers and sense amplifiers are shared between the dual ports to reduce the number of write drivers and sense...
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7287119 |
Integrated circuit memory device with delayed write command processing
An integrated circuit memory device having delayed write command processing includes a first set of pins coupled to a memory core, the first set of pins to receive a row address followed by a...
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7286415 |
Semiconductor memory devices having a dual port mode and methods of operating the same
A memory device having a dual port function includes a memory cell array and a switching unit. The memory cell array has a first port and a second port. The switching unit assigns first data...
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7286394 |
Non-volatile semiconductor memory device allowing concurrent data writing and data reading
A write bit line and a read bit line are provided separately for a memory cell. A source line connecting to the memory cell is formed of a source impurity region the same in conductivity type as a...
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7283403 |
Memory device and method for simultaneously programming and/or reading memory cells on different levels
A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells....
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7280427 |
Data access circuit of semiconductor memory device
A data access circuit of a semiconductor memory device in which data is read and written via all multiple ports in the semiconductor memory device having a multi-port structure. The data access...
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