Matches 1 - 50 out of 782 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >
Match Document Document Title
7391643 Semiconductor memory device and writing method thereof  
To provide a semiconductor memory device comprising a phase-change memory and having high compatibility with DRAM interface. The memory cell array 18 comprises a memory cell that includes a...
RE40356 Large-capacity semiconductor memory with improved layout for sub-amplifiers to increase operational speed  
A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and...
7379383 Methods of DDR receiver read re-synchronization  
A method for reading data is provided. The method includes generating two or more pulses from a first clock signal by which the data to be read is received, using each generated pulse to latch data...
7379380 Low power multi-chip semiconductor memory device and chip enable method thereof  
A multi-chip semiconductor device capable of selectively activating and deactivating the individual semiconductor chips of the device and a chip enable method thereof are provided. The individual...
7376021 Data output circuit and method in DDR synchronous semiconductor device  
Embodiments of the present invention include a data output circuit that can read data in parallel from a plurality of latches in a pipeline circuit. Even-numbered data and odd-numbered data are...
7369448 Input circuit for memory device  
An input circuit for a semiconductor memory device is disclosed. The input circuit controlling transmission paths for data having passed through a data input buffer by using a 1-clock shifted block...
7366031 Memory arrangement and method for addressing a memory  
A memory arrangement includes a plurality of switching elements arranged in the form of a binary tree. The memory elements are supplied with data to be stored by the switching elements coupled to...
7362621 Register file with a selectable keeper circuit  
A register file includes a multi-level multiplexer output circuit coupled to a global bit trace and keeper circuitry coupled to said global bit trace and a driving signal trace. The register file...
7359252 Memory data bus structure and method of transferring information with plural memory banks  
A data bus structure for a dynamic random access memory (DRAM) according to the present invention includes a series of data buses, each shared by a plurality of memory banks, and a switching device...
7355899 Pipe latch circuit of multi-bit prefetch-type semiconductor memory device with improved structure  
Provided is a pipe latch circuit of a multi-bit pre-fetch type semiconductor memory device with an advanced structure. The pipe latch circuit includes: a first latch circuit for simultaneously...
7355881 Memory array with global bitline domino read/write scheme  
A circuit for implementing memory arrays using a global bitline domino read/write scheme. The memory circuit includes a plurality of cells each configured to store a bit of data. The memory circuit...
7353356 High speed, low current consumption FIFO circuit  
A FIFO circuit includes a write counter circuit, a memory circuit, a read counter circuit and a selector circuit. The write counter circuit counts a write clock signal during a valid period of...
7352634 Nonvolatile latch circuit and system on chip with the same  
A nonvolatile latch circuit and a system on a chip with the same feature detection of change of latch data in an active period to store new data in a latch without an additional data storage time....
7349233 Memory device with read data from different banks  
In some embodiments, a chip includes at least four groups of memory banks and at least four groups of output conductors wherein each group of output conductors corresponds to a different one of the...
7339810 Device and method for ensuring current consumption in search engine system  
A search engine system ( 100 ) can include a key multiplexer ( 104 ) and logic circuit ( 108 ). A key from a previous operation can be received by logic circuit ( 108 ) and altered to generate an...
7336554 Semiconductor memory device having a reduced number of pins  
A semiconductor memory device includes an IO circuit for receiving or outputting command signals, address signals and data which are serialized and an IO signal control circuit for parallel...
7333379 Balanced sense amplifier circuits with adjustable transistor body bias  
Structures of balanced sense amplifier circuits and methods for operating the same. The structure comprises a reading circuit, which includes a first transistor and a second transistor. The first...
7330368 Three-dimensional semiconductor device provided with interchip interconnection selection means for electrically isolating interconnections other than selected interchip interconnections  
In a three-dimensional semiconductor device in which a plurality of semiconductor circuit chips are stacked and that is provided with a plurality of interchip interconnections for signal...
7327766 Circuit configuration for receiving a data signal  
In a clock-synchronously operated semiconductor memory, particularly a DDR SDRAM, data are read in clock-synchronously with respect to a data strobe signal in the normal mode, according to...
7324396 Sense amplifier organization for twin cell memory devices  
A semiconductor memory device is provided that uses a single wordline to access both storage cells of a so-called twin cell. A memory device comprises a plurality of wordlines and a plurality of...
7321603 Method and system for reducing bit error rate in a high-speed four to one time domain multiplexer  
Method and system for reducing bit error rate (BER) in a high-speed four-to-one time domain multiplexer are disclosed. In one embodiment of the present invention, a keep-alive current is employed...
7319624 Memory built in self test circuit and method for generating a hardware circuit comprising the routing boxes thereof  
A circuit and a method for performing a memory built in self test (MBIST) are provided. The circuit comprises a plurality of routing boxes and a test controller. The test controller provides test...
7319622 Bitline shielding for thyristor-based memory  
Method and apparatus for writing and reading information to and from a memory cell. For a read, a write path is used to electrically shield at least one adjacent bitline from a bitline associated...
7317644 Signal timing for I/O  
Circuits, methods, and apparatus for ordering the timing of clock and data signals. Programmable delay cells are utilized in a data output cell to control a critical multiple data rate input/output...
7313018 Methods and apparatus for a non-volatile memory device with reduced program disturb  
A non-volatile memory device includes a plurality of power control circuits interfaced via a single Y multiplexer with an array of memory cells. The multiple power control circuits provide multiple...
7310281 Semiconductor memories with refreshing cycles  
The present invention discloses a semiconductor memory having an array of storage cells with at least one PMOS transistor, the semiconductor memory comprising at least one mode bit for representing...
7301826 Memory, processing system and methods for use therewith  
A memory includes a selected bitline coupled to the array of memory cells. A column voltage booster produces a boosted column enable signal. A column multiplexer passes a signal on the selected...
7301824 Method and apparatus for communication within an integrated circuit  
Method and apparatus for communication within an integrated circuit is described. In one example, an integrated circuit includes a first logic circuit, a second logic circuit, first...
7301798 Random access memory cell of reduced size and complexity  
A memory cell ( 1 ), includes a flip-flop ( 2 ) that has additional read/write terminals; a 1-bit write line (wb 11 ); a first transistor (T 4 ) switching between the 1-bit write line and the...
7292498 Factored nanoscale multiplexer/demultiplexer circuit for interfacing nanowires with microscale and sub-microscale electronic devices  
Embodiments of the present invention are related to nanoscale multiplexers and demultiplexers that employ randomly fabricated interconnections between nanowire signal lines and microscale or...
7292479 Memory device with multistage sense amplifier  
A memory device with a multistage sense amplifier is disclosed. According to one aspect, a memory device has a memory cell array having at least one memory cell, at least one sense amplifier....
7289379 Memory devices and methods of operation thereof using interdependent sense amplifier control  
A memory device includes a control circuit configured to disable a local input/output line sense amplifier responsive to a global input/output line sense amplifier enable signal. The device may...
7289373 High performance memory device  
A memory device is provided comprising a memory array consisting of a plurality of memory cells. These memory cells are accessed via a plurality of word lines and a plurality of bit lines....
7286416 Non-volatile semiconductor memory device and semiconductor memory device  
For each memory block, a predecoder for predecoding an applied address signal, an address latch circuit for latching the output signal of the predecoder, and a decode circuit for decoding an output...
7286415 Semiconductor memory devices having a dual port mode and methods of operating the same  
A memory device having a dual port function includes a memory cell array and a switching unit. The memory cell array has a first port and a second port. The switching unit assigns first data...
7280413 Nonvolatile semiconductor memory  
A transmission transistor transmitting a drain voltage is connected to an electrically rewritable nonvolatile memory cell. An operation control circuit controls program operation for increasing a...
7272056 Data output controller in semiconductor memory device and control method thereof  
A data output controller of a high-speed memory device and a method therefore. The data output controller includes a first section for detecting a unit delay multiple of an external clock signal...
7269089 Divisible true dual port memory system supporting simple dual port memory subsystems  
A random access memory circuit and a method for configuring the same. The circuit includes a first array of memory cells including a first plurality of ports and a second plurality of ports, and a...
7266020 Method and apparatus for address and data line usage in a multiple context programmable logic device  
A method and apparatus to provide triple modular redundancy (TMR) in one mode of operation, while providing multiple context selection during a second mode of operation. Intelligent voting...
7263011 Memory circuit with flexible bitline-related and/or wordline-related defect memory cell substitution  
The inventive memory circuit comprises a main memory block and a substitution memory block for substitution of defect memory cells, with the substitution memory block being external to the main...
7257036 Method and apparatus for storage device read phase auto-calibration  
The present invention provides a method and apparatus for performing read phase auto-calibration of a storage device. The method includes writing the data with at least one predetermined pattern...
7257013 Method for writing data into a memory cell of a conductive bridging random access memory, memory circuit and CBRAM memory circuit  
The present invention refers to a method for writing data into a memory cell of a conductive bridging random access memory and to a memory circuit comprising memory cells with programmable...
7251715 Double data rate scheme for data output  
Systems, devices, and methods for a double data rate memory device includes a storage element, a first pipeline, and a second pipeline. The pipelines are connected to the storage unit to pass or...
7251180 Semiconductor memory device  
An apparatus a counter, storage units for storing count values interrupted by a row address whose refresh period is subject to change; comparator circuits for comparing the counter outputs and the...
7251171 Semiconductor memory and system apparatus  
A register part of a mode register has a plurality of operation setting parts in which plural types of operating specifications are respectively set to operate the semiconductor memory. The mode...
7236421 Read-modify-write memory using read-or-write banks  
Minimal memory access times are realized by using a single access to a read-modify-write bank. read-modify-write memory including at least one read-or-write bank is operated in a manner that uses...
7230872 Efficent column redundancy techniques  
The present invention relates to a system and method adapted to increase memory cell and memory architecture design yield. The present invention includes memory architecture having a decoder and a...
7230865 Input/output line sharing apparatus of semiconductor memory device  
Provided is an input/output line sharing apparatus of a semiconductor memory device. In this apparatus, a global input/output line is shared by a data line signal and a test mode signal, and an...
7230856 High-speed multiplexer latch  
Embodiments of a high-speed multiplexer latch are described. The multiplexer latch may include a multiplexer and a latch coupled to each other at a first node and a second node. The multiplexer...
7225306 Efficient address generation for Forney's modular periodic interleavers  
An efficient way to generate the address sequence for the RAM implementation of Forney's (P, D, m) interleavers requires only A+1+2P memory locations, which is close to the theoretical minimum....
Matches 1 - 50 out of 782 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >