Matches 301 - 350 out of 866 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >
Match Document Document Title
6711067 System and method for bit line sharing  
A system and method is provided for bit line sharing in a memory device. Adjacent memory cells are configured to share a bit line and are accessed with separate word lines as an odd and even plane....
6711077 Wafer burn-in test and wafer test circuit  
A wafer burn-in test and a wafer test circuit for a semiconductor memory device which can cut down packaging expenses and improve F/T yield by performing a wafer burn-in test by using a pad for...
6711068 Balanced load memory and method of operation  
A memory provides a sensing scheme that maintains impedance balance between the route that the data takes to the sense amplifier and the route the reference or references take to the sense...
6704243 Apparatus for generating memory-internal command signals from a memory operation command  
A device for generating memory-internal command signals from a memory operation command includes a command input for receiving a memory operation command for performing a memory operation in a...
6704232 Performance for ICs with memory cells  
An integrated memory device comprises a multitude of sense amplifiers which output an amplified data signal on a data line. The data line is forced to a precharge potential when idle. A transistor...
6700823 Programmable common mode termination for input/output circuits  
Systems and methods provide common mode termination for input/output circuits. For example, common mode termination may be provided to a bank of input/output circuits by programmably coupling a bus...
6697275 Method and apparatus for content addressable memory test mode  
A content addressable memory (CAM) ( 100 ) can include a number of CAM entries ( 102 - 0 to 102 -n). Match indications from CAM entries ( 102 - 0 to 102 -n) and mismatch indications from...
6681286 Control chipset having dual-definition pins for reducing circuit layout of memory slot  
A control chipset having dual-definition data pins capable of reducing circuit layout to memory module slots. Using dual-definition data pins of the control chipset and multiplexing/de-multiplexing...
6680871 Method and apparatus for testing memory embedded in mask-programmable logic device  
In a mask-programmable logic device having embedded memory blocks, which device cannot be reconfigured for testing like a full programmable logic device, the embedded memory blocks are tested by...
6667895 Integrated circuit device and module with integrated circuits  
An integrated circuit comprises a substrate having circuitry integrated with the substrate. Switching circuitry is selectably operable to configure signal paths to alternative mirrored pads over...
6661726 Multiple mode elastic data transfer interface  
Space, power and performance are improved by a memory device having multiple modes of operation for elastic data transfer. The memory device is comprised of first and second elastic store memory...
6657901 Semiconductor device formed in a rectangle region on a semiconductor substrate including a voltage generating circuit  
A semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and...
6646928 Packet-based integrated circuit dynamic random access memory device incorporating an on-chip row register cache to reduce data access latencies  
A packet-based dynamic random access memory (“DRAM”) device incorporating an on-chip row register cache which is functional to reduce the initial device latency, reduce “page miss” latency...
6646956 One-shot signal generating circuit  
A one-shot signal generation circuit is provided which makes it easy to adjust pulse width and to deal with variation of skew of an ATD signal, and can reduce chip area. A timing determination...
6625075 Multilevel DRAM sensing analog-to-digital converter  
A method for performing a sense and restore operation in a multilevel DRAM is described. The method describes the selective enabling of the sense amplifiers to operate at predetermined sensing...
6625069 Data path decoding technique for an embedded memory array  
A data path decoding technique and architecture for integrated circuit memory devices and those devices incorporating embedded dynamic random access memory (“DRAM”) arrays provides an effective...
6614711 Row decoder scheme for flash memory devices  
Devices and methods for enhancing decoding a non-volatile memory device are discussed. One aspect of the present invention includes a method for decoding a non-volatile memory device. The method...
6614697 Diode-based multiplexer  
A multiplexer includes a plurality of stages. Each stage includes a storage device coupled to a data output; a first diode coupled between a data input and a power supply input; and a second diode...
6611040 Anti-fuse structure of writing and reading in integrated circuits  
An information write-register embedded in an integrated circuit (IC) is made of a plurality of independently addressable gate-controlled components formed in an isolated p-well nested in a n-well....
6603686 Semiconductor memory device having different data rates in read operation and write operation  
A semiconductor memory device and a system using the semiconductor memory device can perform a data sampling operation safely without a phase synchronization device such as delay locked loop (DLL)...
6600693 Method and circuit for driving quad data rate synchronous semiconductor memory device  
The present invention discloses a method and circuit for driving a word line and a bit line for a read/write operation of a quad data rate synchronous semiconductor memory device which can perform...
6600686 Apparatus for recognizing chip identification and semiconductor device comprising the apparatus  
A semiconductor device having an apparatus is provided for recognizing chip identification capable of minimizing the number of pads. The apparatus for recognizing chip identification comprises a...
6594179 Floating gate type nonvolatile semiconductor memory  
In a floating gate type nonvolatile semiconductor memory having a memory cell array constituted of a plurality of memory cells arrayed in a matrix pattern, word lines and bit lines, with the word...
6584023 System for implementing a column redundancy scheme for arrays with controls that span multiple data bits  
An exemplary embodiment of the present invention is a system for implementing a column redundancy scheme for arrays with controls that span multiple data bits. The system includes an array of data...
6580648 Memory circuit  
The present invention relates to a memory having sense amplifiers and data latches, the data latches being used in a test mode to form a signature register. In a normal operation mode, the data...
6577554 Semiconductor memory device for providing margin of data setup time and data hold time of data terminal  
A semiconductor memory device secures a margin of data setup time and hold time of a data terminal and includes a delay locked loop, an output replica, an output driver, and an output multiplexer....
6573748 Programmable logic device with output register for specifying memory space during reconfiguration  
Described are programmable logic systems and methods in which programmable logic devices receive configuration data. In some embodiments, one or more input/output blocks of a programmable logic...
6574163 Semiconductor memory device with single clock signal line  
A semiconductor memory device includes two memory cell array sections, a single clock signal line, a clock signal generating section and a multiplexer section. The clock signal generating section...
6570814 Integrated circuit device which outputs data after a latency period transpires  
An integrated circuit device which includes an array of dynamic memory cells. The integrated circuit device comprises an input receiver to sample an operation code synchronously with respect to a...
6570809 Real-time multitasking flash memory with quick data duplication  
A flash memory device that is capable of quick data duplication by utilizing a plurality of memory sections. The memory sections each include an address multiplexer, a data multiplexer, and a page...
6567320 Data write circuit  
A data write circuit is interposed between a CPU and memory, both of which operate based on the same number of bits (e.g., thirty-two bits). The CPU produces address data for designating a specific...
6567323 Memory circuit redundancy control  
A memory having flexible column redundancy and flexible row redundancy plural column sticks, each column stick comprising a plurality of data lines. Positioned on either side of the memory are...
6567317 Controlling output current rambus DRAM  
Disclosed is a circuit for controlling output currents of the data ports in a Rambus DRAM having two data ports DQA and DQB. The disclosed circuit arrangements save power and require less chip...
6563745 Memory device and method for dynamic bit inversion  
A memory device and method for storing bits in a memory array is provided. In one preferred embodiment, a memory device is provided comprising a plurality of memory cells that are in a first...
6564281 Synchronous memory device having automatic precharge  
A synchronous memory device including an array of memory cells. The memory device includes a plurality of sense amplifiers, coupled to the array of memory cells, to sense data. The memory device...
6563743 Semiconductor device having dummy cells and semiconductor device having dummy cells for redundancy  
A dummy cell includes a plurality of first memory cells MC for storing “1” or “0”, arranged at points of intersection between a plurality of word lines WR 0 to WR 7 and a plurality of...
RE38109 Block write circuit and method for wide data path memory device  
A block write circuit in a memory device having a wide internal data path performs block write and data masking functions. The memory device includes a plurality of data terminals adapted to...
6556504 Nonvolatile semiconductor memory device and data input/output control method thereof  
A nonvolatile semiconductor memory device comprises an address buffer, a column address register, a selection circuit, a data input/output circuit, and a controller. The controller controls the...
6556500 Programmable logic array device with random access memory configurable as product terms  
A look-up-table-based programmable logic device is provided with memory circuitry which can be operated either as random access memory (“RAM”) or to perform product term (“p-term”) logic....
6556490 System and method for redundancy implementation in a semiconductor device  
A system and method for redundancy implementation in an integrated semiconductor device having at least one memory instance that includes a prime memory array and a redundant portion. A fuse box...
6552952 Column multiplexer for semiconductor memories  
The column multiplexer is for a memory matrix having memory cells arranged in rows and columns. The multiplexer includes input lines for input signals, a plurality of output lines for electrical...
6549444 Memory device with prefetched data ordering distributed in prefetched data path logic, circuit, and method of ordering prefetched data  
A memory device is adapted for prefetching data. The memory device has a memory cell array, with local sense amplifiers for receiving data bits prefetched from the memory cell array. The memory...
6549475 Semiconductor memory device and information device  
A semiconductor memory device in which an input command controls an operation includes a command state machine for decoding the input command and outputting the decoding result; a plurality of...
6549472 Packet-based integrated circuit dynamic random access memory device incorporating an on-chip row register cache to reduce data access latencies  
A packet-based dynamic random access memory (“DRAM”) device incorporating an on-chip row register cache which is functional to reduce the initial device latency, reduce “page miss” latency...
6545909 Nonvolatile semiconductor memory device  
A memory cell array in which memory cells storable multilevel data are arranged in a matrix. Bit line controllers have latch circuits configured to latch write data and sense circuits configured to...
6546461 Multi-port cache memory devices and FIFO memory devices having multi-port cache memory devices therein  
A FIFO memory device includes an embedded memory array having a write port and a read port and a quad-port cache memory device. The cache memory device has a unidirectional data input port, a...
6538950 Integrated memory and corresponding operating method  
An integrated memory has a multiplexer and a differential sense amplifier with a differential input. The differential sense amplifier is connected to three bit lines by the multiplexer. The...
6529428 Multi-bit parallel testing for memory devices  
A method and apparatus for testing memory devices. One embodiment provides a method including receiving a first input data bit having a first polarity, and receiving a second input data bit having...
6529040 FPGA lookup table with speed read decoder  
A fast, space-efficient lookup table (LUT) for programmable logic devices (PLDs) in which the write decoder, read decoder and memory block of the LUT are modified to improve performance while...
6529419 Apparatus for varying data input/output path in semiconductor memory device  
An apparatus for varying a data input/output path in a memory device, includes DBSAs amplifying a signal loaded on a data bus, fuse circuits producing output signals of specific levels respectively...
Matches 301 - 350 out of 866 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >