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7024498 Apparatus for receiving data packet eliminating the need of a temporary memory and memory controller and method thereof  
A device for effectively and economically receiving a packet by eliminating temporary memory and a memory controller. The apparatus includes an inspection logic circuit for inspecting data units as...
7016235 Data sorting in memories  
A sorting circuit ( 140 ) transfers data between a first group of at least four lines ( 134 ) on which the data items are arranged based on their addresses, and a second group of lines ( 138 , WD 0...
7016988 Output buffer register, electronic circuit and method for delivering signals using same  
An output buffer register includes a first input flip-flop register receiving a given number N of input signals, a latching register, a selection register, and an output multiplexer delivering N...
7009423 Programmable I/O interfaces for FPGAs and other PLDs  
A programmable logic device (PLD), such as a field programmable gate array (FPGA) has a logic core surrounded on one or more sides by an input/output (I/O) interface having one or more programmable...
7009880 Non-volatile memory architecture to improve read performance  
A memory cell array is physically divided into an even number of sectors, with each pair of sectors sharing read circuitry. The outputs of the shared read circuitry are commonly connected to form...
7006387 Semiconductor memory device with adjustable I/O bandwidth  
A semiconductor memory device with adjustable I/O bandwidth includes a plurality of data I/O buffers connected one by one to a plurality of I/O ports, a switch array including a plurality of...
7002860 Multilevel register-file bit-read method and apparatus  
A bit-read apparatus includes a first decoder and N multiplexers, each having Q output nodes and Q pull-ups coupled thereto. Respective multiplexers have M selectors coupled to N×M respective...
7002852 Data output circuits for synchronous integrated circuit memory devices  
A data output circuit includes a plurality of registers and a plurality of register output selection switches that are respectively connected to the plurality of registers. Pairs of the plurality...
6987704 Synchronous semiconductor memory device with input-data controller advantageous to low power and high frequency  
There is provided a synchronous memory device having a simplified data input unit for receiving and transferring data to an internal memory cell block, which is adapted to high frequency and can...
6980479 Semiconductor device for domain crossing  
An apparatus, for use in a semiconductor device, for providing a domain crossing operation. The apparatus includes a domain crossing sensing block, in response to an operation mode signal, first...
6980453 Flash memory with RDRAM interface  
A flash memory has been described that has an interface corresponding to a rambus dynamic random access memory (RDRAM). The memory samples commands and addresses on a rising edge of a clock signal....
6978408 Generating array bit-fail maps without a tester using on-chip trace arrays  
An existing trace array on a chip is used to store the locations of bit failures from the automatic self-testing of an SRAM array. If a system is having problems, a technician can trigger the...
6975554 Method and system for providing a shared write driver  
A method for providing a shared write driver is provided. The method includes providing a write driver for a memory array. The memory array comprises a plurality of memory columns. The write driver...
6975558 Integrated circuit device  
An integrated circuit device is disclosed. In one particular exemplary embodiment, the integrated circuit device may comprise a first circuit to receive, in a multiplexed format, control...
6972978 Content addressable memory (CAM) devices with block select and pipelined virtual sector look-up control and methods of operating same  
A CAM array block is configured to perform a search operation in a staged segment-to-segment manner using a plurality of hybrid comparands that are pipelined into the CAM array block during...
6965539 Write path scheme in synchronous DRAM  
A write path scheme in a synchronous DRAM having: a data converter unit to convert serial input data to parallel output data, a multiplexer to output data from the data converter unit depending on...
6956775 Write pointer error recovery  
A write pointer ( 21 ) from a write pointer circuit ( 13 ) may cause a demultiplexer circuit ( 12 ) to direct data from a memory cell ( 11 A– 11 N) to a desired bit location ( 0–4 ) in a...
6947305 Method for fabricating and identifying integrated circuits and self-identifying integrated circuits  
Two types of topologically different three-dimensional integrated circuits (for example a 4-layer three-dimensional memory array and an 8-layer three-dimensional memory array) are fabricated from a...
6947340 Memory device for reducing skew of data and address  
A semiconductor memory device operates at a high speed regardless of variance of power voltage or process change, by consistently keeping variance of the skew between the transfer path of the...
6944040 Programmable delay circuit within a content addressable memory  
An apparatus having an output register coupled to a content addressable memory (CAM) array. The output register may be configured to output data based on a delayed clock signal. A programmable...
6937493 Programming flash memory via a boundary scan register  
A method and parallel interface for on-board programming and/or In-System Configuration of a flash memory mounted on a printed circuit board by controlling its inputs with the aid of an ASIC...
6937530 Delay locked loop “ACTIVE Command” reactor  
A delay locked loop (DLL) that applies an amount of delay to an external clock signal to generate multiple delayed signals. One of the delayed signals is selected as an internal clock signal. The...
6930953 Self-timed strobe generator and method for use with multi-strobe random access memories to increase memory bandwidth  
A circuit takes a reference strobe signal as a first input, and a strobe ready signal generated from a memory that is strobed by the reference strobe signal as a second input. The circuit generates...
6930929 Simultaneous read-write memory cell at the bit level for a graphics display  
An improved memory for graphics displays includes an improved memory cell. Data may be written and read from the single bit cell simultaneously, eliminating the need for additional memory circuits...
6928027 Virtual dual-port synchronous RAM architecture  
Disclosed is a virtual dual-port synchronous RAM device, system, and method, wherein the design requires minimal hardware cost compared with a dual-port RAM architecture or the traditional...
6928024 RAM memory circuit and method for memory operation at a multiplied data rate  
A RAM memory circuit has at least one memory bank with a multiplicity of memory cells arranged like a matrix in rows and columns and is subdivided into q≧2 areas, each of which comprises p≧1...
6928025 Synchronous integrated memory  
An output circuit (OUT) can be activated via an activation input (AKT), in the activated state starts an output process for data (D) to be read out, in synchronism with the first internal clock...
6925015 Stacked memory device having shared bitlines and method of making the same  
Briefly, in accordance with one embodiment of the invention, a system includes a memory array. The memory array comprises a first layer of memory cells overlying a second layer of memory cells and...
6924663 Programmable logic device with ferroelectric configuration memories  
A programmable logic device with ferroelectric configuration memories storing multiple configuration data sets. The device has programmable logic blocks, interconnections, and I/O blocks to provide...
6920068 Semiconductor memory device with modified global input/output scheme  
A semiconductor memory device including a main amplifier for amplifying an output from a bit line sensing amplifier and outputting the amplified output to a first data line; an input/output...
6917563 Integrated memory  
An integrated memory contains an access controller for controlling an access for the purpose of reading data from, or writing data to, a memory cell array. The access controller accesses the memory...
6914450 Register-file bit-read method and apparatus  
A register-file bit read apparatus includes a decoder operable to receive a number of address-bit signals and responsively assert a select signal on one of M select lines. Each select line...
6914829 Multi-stage output multiplexing circuits and methods for double data rate synchronous memory devices  
An output multiplexing circuit for a Double Data Rate (DDR) synchronous memory device includes n first latches, n first switches, n second switches, n second latches, and two third switches. The n...
6914844 Deep power down switch for memory device  
A circuit to operate a semiconductor integrated circuit memory device having memory cells in a deep power down mode. The power down circuit includes a transistor switch connected between an...
6912164 Techniques for preloading data into memory on programmable circuits  
Techniques for preloading data into memory blocks on a programmable circuit are provided. Memory blocks on the a programmable circuit each have dedicated circuitry that loads data into the memory...
6901490 Read/modify/write registers  
The present invention may provide a digital memory circuit comprising a plurality of multi-bit registers, a memory circuit interface, and a logic circuit. The memory circuit interface may be...
6898139 Integrated circuit memory devices and operating methods that are configured to output data bits at a lower rate in a test mode of operation  
Integrated circuit memory devices include a memory cell array that is configured to output data bits in parallel at a first data rate. An output circuit is configured to serially output the data...
6891774 Delay line and output clock generator using same  
A delay line for an adjustable, high speed clock generator is based on two-stage multiplexing, in which for all pairs of adjacent taps, a change from a current tap to an adjacent tap in the pair is...
6888730 Content addressable memory cell  
A content addressable memory (CAM) having a plurality of ternary memory cells, each ternary half cell comprising an equal number of transistors of a p-type and an n-type, the p-type transistors...
6885610 Programmable delay for self-timed-margin  
A system and method for adjusting the clock delay in a self-timed memory system having a memory array and a sense amplifier includes a programmable delay circuit coupled as an input to the sense...
6882589 Prefetch buffer  
A computer system comprising a plurality of data processing elements connected through a shared communication bus to a memory so that for a given computer cycle at least one of the elements assumes...
6879527 Semiconductor memory device with structure providing increased operating speed  
A semiconductor memory device includes a plurality of memory array blocks including predetermined numbers of memory cells, the memory array blocks being arranged in the row direction; a RAS chain...
6879535 Approach for zero dummy byte flash memory read operation  
A nonvolatile memory device, in a continuous read operation, requires no dummy bytes between receipt of a read command and commencement of a scanning out of a first target data byte. The highest...
6880094 Cas latency select utilizing multilevel signaling  
A method of selecting CAS latencies in a system. Specifically, a system which includes a plurality of memory modules is provided. Because different memory modules may have different CAS latencies,...
6876563 Method for configuring chip selects in memories  
Embodiments of the present invention relate to an electronic device having programmable chip enable inputs in that each chip enable has a programmable assertion level, e.g., high or low. The device...
6876567 Ferroelectric memory device and method of reading a ferroelectric memory  
A ferroelectric memory device comprises a plurality of subarrays having a plurality of bitlines and a plurality of wordlines crossing over the bitlines. Ferroelectric material is disposed between...
6870782 Row redundancy memory repair scheme with shift to eliminate timing penalty  
A memory having built-in self repair with row shifting is provided. The rows in the memory are divided into smaller row groups and a bad row group is repaired with a redundant row group. Each row...
6870775 System and method for small read only data  
A system and method is provided for minimizing read-only data retrieval time and/or area through the use of combinatorial logic. In one embodiment of the present invention, two address bits are...
6862224 System and method for operating a memory array  
A method and apparatus for storing and retrieving data in a second, or higher, order prefetch architecture memory integrated circuit. The method includes storing multiple bits of data in memory...
6862230 Efficient column redundancy techniques  
The present invention relates to a system and method adapted to increase memory cell and memory architecture design yield. The present invention includes memory architecture having a decoder and a...
Matches 201 - 250 out of 866 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >