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7151699 |
Semiconductor memory device
Provided is a semiconductor memory device, which is capable of further simplifying the data multiplexing structure on a data write path, thereby preventing a timing mismatch in data input from...
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7151709 |
Memory device and method having programmable address configurations
A memory device includes a configurable address register having a first set of input buffers coupled to a first set on address bus terminals and a second set of input buffers coupled to a second...
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7149129 |
Memory output data systems and methods with feedback
Systems and methods provide output data from a memory. For example, in accordance with an embodiment of the present invention, techniques are disclosed for providing glitch-free output data from a...
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7145810 |
High density memory and multiplexer control circuit for use therein
A high density memory is disclosed wherein multiple memory cells are placed in a single cell region. To accommodate the multiple memory cells, multiple bit lines are provided. Also provided is a...
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7145831 |
Data synchronization arrangement
A data synchronization arrangement is provided that is fail-safe at high speed and low power consumption, for exchanging clocked data between different clock domains running in a digital processing...
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7136309 |
FIFO with multiple data inputs and method thereof
A FIFO circuit includes a memory such as a register array having a plurality of storage locations. One or more data inputs can be coupled to the memory for receiving data that is to be stored...
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7136311 |
Level shifter, level shift circuit, electro-optical device, and electronic apparatus
To provide a level shift circuit which has reduced power consumption. A level shift circuit includes level shifters and a control unit. The control unit generates control signals for controlling...
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7133324 |
Synchronous dynamic random access memory devices having dual data rate 1 (DDR1) and DDR2 modes of operation and methods of operating same
A dual data rate dynamic random access memory (DDR DRAM) device may operate in dual DDR modes via a mode selection circuit configured to enable a Dual Data Rate (DDR) 1 mode of operation for the...
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7130238 |
Divisible true dual port memory system supporting simple dual port memory subsystems
A random access memory circuit and a method for configuring the same. The circuit includes a first array of memory cells including a first plurality of ports and a second plurality of ports, and a...
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7126858 |
Apparatus for emulating asynchronous clear in memory structure and method for implementing the same
Circuitry is disclosed for emulating asynchronous clear on each of a read address register of a memory cell and a data output register of a memory cell such that the memory cell can be defined in a...
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7120075 |
Multi-FIFO integrated circuit devices that support multi-queue operating modes with enhanced write path and read path queue switching
An integrated circuit chip includes a plurality of independent FIFO memory devices that are each configured to support all four combinations of DDR and SDR write modes and DDR and SDR read modes...
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7120066 |
Memory device for multiplexing input and output operation
A memory device for multiplexing an input/output operation prevents mis-operations by comparing the input addresses with the output data and improves operating speed by activating data...
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7120761 |
Multi-port memory based on DRAM core
A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum...
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7110321 |
Multi-bank integrated circuit memory devices having high-speed memory access timing
Integrated circuit memory devices support write and read burst modes of operation with uniformly short interconnect paths that provide high-speed memory access timing characteristics. These memory...
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7110305 |
Nonvolatile semiconductor memory device for outputting a status signal having an output data width wider than an input data width
An n-bit status signal indicating an execution state of a write command is outputted from a status register. At the time of data writing, an output switching circuit outputs (n×m)-bit data in...
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7110304 |
Dual port memory array using shared write drivers and read sense amplifiers
Dual port memory blocks that have a reduced layout area are provided. The write drivers and sense amplifiers are shared between the dual ports to reduce the number of write drivers and sense...
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7106632 |
Integrated circuit with analog or multilevel storage cells and user-selectable sampling frequency
Techniques are used to store information in a medium such as the memory cells of an integrated circuit, and also retrieval of information from the medium. The integrated circuit includes...
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7106633 |
Write pointer error recovery systems and methods
Write pointer error recovery systems and methods are provided. A write pointer from a write pointer circuit may cause a demultiplexer circuit to direct data from a memory cell to a desired bit...
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7102917 |
Memory array method and system
An MRAM memory array includes a set of memory cell strings wherein each memory cell string has a voltage divider input, a bit-sense output, a voltage divider ground, and a bit-sense output control,...
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7099231 |
Interleaving memory blocks to relieve timing bottleneck in a multi-queue first-in first-out memory system
A multi-queue memory system includes first and second memory blocks. The first memory block includes a first array of memory cells, a first sense amplifier circuit and a second sense amplifier...
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7099202 |
Y-mux splitting scheme
A multiplexer circuit in a memory organized into page-portions has a plurality of bit-select multiplexers configured to couple a plurality of page-portion global bitlines to a sense amplifier...
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7095641 |
Content addressable memory (CAM) devices having priority class detectors therein that perform local encoding of match line signals
Content addressable memory devices may include a priority encoder therein and a first tier of CAM arrays arranged side-by-side relative to each other, on a first side of the priority encoder. A...
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7095658 |
Flash memory data bus for synchronous burst read page
Memory device is described that utilizes a reduced number of sense amplifiers to sense the data bits of a selected column page. The sense amplifiers are multiplexed and the read data values...
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7093095 |
Double data rate scheme for data output
Systems, devices, and methods for a double data rate memory device includes a storage element, a first pipeline, and a second pipeline. The pipelines are connected to the storage unit to pass or...
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7092310 |
Memory array with multiple read ports
A multiport array comprises a read section which is separated from an array of memory cells and which forms a plurality of data-out ports each consisting of a predetermined number of output lines....
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7088627 |
Column redundancy scheme for non-volatile flash memory using JTAG input protocol
A JTAG-programmable IC includes a memory array having redundant columns, a partial-width data register, and a full-width bitline register. A programming bitstream is shifted into the data register...
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7088624 |
System of multiplexed data lines in a dynamic random access memory
A system of multiplexed data lines in a DRAM integrated circuit includes a switching circuit having two switching states. In one switching state, the data lines connect to a first configuration of...
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7079431 |
Arrangement with a memory for storing data
An arrangement with a memory for storing data has a first memory for storing data, switching devices which stipulate whether access to the first memory involves output of the data stored in the...
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7079426 |
Dynamic multi-Vcc scheme for SRAM cell stability control
A dynamic multi-voltage memory array features SRAM cells that are subjected to different biasing conditions, depending on the operating mode of the cells. The selected SRAM cell receives a first...
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7079445 |
Flash memory pipelined burst read operation circuit, method, and system
Method and apparatus for use with flash memory devices and systems are included among the embodiments. In exemplary systems, a pipelined burst read operation allows the device to support higher...
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7075850 |
Compact decode and multiplexing circuitry for a multi-port memory having a common memory interface
A memory array for a multi-port memory having a common memory interface and a plurality of memory ports through which the memory array is accessed is provided. The memory array includes (r•s•t)...
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7075821 |
Apparatus and method for a one-phase write to a one-transistor memory cell array
A method and apparatus for a one-phase write to a one-transistor memory cell array. In one embodiment, the method includes a one-phase write to a selected wordline of a memory cell array. Once the...
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7071731 |
Programmable Logic with Pipelined Memory Operation
Memory performance of an integrated circuit, such as a programmable logic integrated circuit, is increased by pipelining. In a single clock cycle, more than one operation may be performed on the...
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7073035 |
Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules
Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules are disclosed. In one exemplary embodiment, the techniques are realized through a memory...
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7072227 |
Current mode output driver
A current mode output driver and output current control method of controlling an output current using a gate voltage are provided. The current mode output driver, which outputs data read from a...
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7068567 |
Data output controller in semiconductor memory device and control method thereof
A data output controller of a high-speed memory device and a method therefor. The data output controller includes a first section for detecting a unit delay multiple of an external clock signal...
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7069464 |
Hybrid parallel/serial bus interface
A hybrid serial/parallel bus interface has a data block demultiplexing device. The data block demultiplexing device has an input configured to receive a data block and demultiplexes the data block...
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7064571 |
Multiple-select multiplexer circuit, semiconductor memory device including a multiplexer circuit and method of testing the semiconductor memory device
A multiplexer circuit is composed of several basic unit circuits, which are each supplied with a data signal and select signal. Each output terminal of several basic unit circuits is connected to a...
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7064990 |
Method and apparatus for implementing multiple column redundancy for memory
An apparatus for implementing multiple memory column redundancy within an individual memory array includes a plurality of memory array elements internally partitioned into at least a pair of...
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7054224 |
Non-synchronous semiconductor memory device having page mode read/write
The present invention provides a non-synchronous semiconductor memory device configured as a pseudo-SRAM and capable of relaxing the limitation to address skew and improving the read rate. A data...
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7054214 |
Semiconductor device
A dummy cell includes a plurality of first memory cells MC for storing “1” or “0”, arranged at points of intersection between a plurality of word lines WR 0 to WR 7 and a plurality of...
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7054205 |
Circuit and method for determining integrated circuit propagation delay
A circuit and method is provided for determining the delay of an integrated circuit common associated with chip-to-chip variations in the manufacturing process, changes in operating voltage, and...
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7042799 |
Write circuit of double data rate synchronous DRAM
Provided is a write circuit of a DDR SDRAM, in which a clock domain crossing is generated from a writing driver during a data write operation and a proper data is always transferred to a gio bus...
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7038952 |
Block RAM with embedded FIFO buffer
A programmable logic device includes a block random access memory (“BRAM”) with an embedded first in, first out (“FIFO”) controller. Embedding the FIFO logic in silicon, rather than...
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7038932 |
High reliability area efficient non-volatile configuration data storage for ferroelectric memories
Configuration data is stored in one or more rows of non-volatile ferroelectric memory cells, where these rows are formed adjacent to rows of a primary memory array. The primary memory array...
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7035164 |
Semiconductor memory device with a bypass circuit for verifying the characteristics of an internal clock signal
A semiconductor memory device comprising a bypass circuit for verifying the characteristics of an internal clock signal is provided. The semiconductor memory device having a bypass circuit for...
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7031204 |
Low power register apparatus having a two-way gating structure and method thereof
A register apparatus and method for providing a two-way gating structure for receiving a write enable signal, a chip select signal, at least one read signal, and an address signal for a register....
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7031211 |
Direct memory access interface in integrated circuits
A direct memory access interface incorporates setting bit line selection data into a particular storage element of a desired page register element. The selection data and an access enable signal...
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7031201 |
Semiconductor memory device with late write function and data input/output method therefor
An integrated circuit memory device includes a memory cell array, a plurality of data input lines configured to convey data to the memory cell array and a plurality of data output lines configured...
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7027344 |
High-speed semiconductor memory having internal refresh control
The refresh address generator of a memory includes, in part, a counter, a multitude of shift registers and multiplexers, and a comparator. With each clock cycle, the counter increments and stores...
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