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7330368 Three-dimensional semiconductor device provided with interchip interconnection selection means for electrically isolating interconnections other than selected interchip interconnections  
In a three-dimensional semiconductor device in which a plurality of semiconductor circuit chips are stacked and that is provided with a plurality of interchip interconnections for signal...
7327766 Circuit configuration for receiving a data signal  
In a clock-synchronously operated semiconductor memory, particularly a DDR SDRAM, data are read in clock-synchronously with respect to a data strobe signal in the normal mode, according to...
7324396 Sense amplifier organization for twin cell memory devices  
A semiconductor memory device is provided that uses a single wordline to access both storage cells of a so-called twin cell. A memory device comprises a plurality of wordlines and a plurality of...
7321603 Method and system for reducing bit error rate in a high-speed four to one time domain multiplexer  
Method and system for reducing bit error rate (BER) in a high-speed four-to-one time domain multiplexer are disclosed. In one embodiment of the present invention, a keep-alive current is employed...
7319622 Bitline shielding for thyristor-based memory  
Method and apparatus for writing and reading information to and from a memory cell. For a read, a write path is used to electrically shield at least one adjacent bitline from a bitline associated...
7319624 Memory built in self test circuit and method for generating a hardware circuit comprising the routing boxes thereof  
A circuit and a method for performing a memory built in self test (MBIST) are provided. The circuit comprises a plurality of routing boxes and a test controller. The test controller provides test...
7317644 Signal timing for I/O  
Circuits, methods, and apparatus for ordering the timing of clock and data signals. Programmable delay cells are utilized in a data output cell to control a critical multiple data rate input/output...
7313018 Methods and apparatus for a non-volatile memory device with reduced program disturb  
A non-volatile memory device includes a plurality of power control circuits interfaced via a single Y multiplexer with an array of memory cells. The multiple power control circuits provide multiple...
7310281 Semiconductor memories with refreshing cycles  
The present invention discloses a semiconductor memory having an array of storage cells with at least one PMOS transistor, the semiconductor memory comprising at least one mode bit for representing...
7301826 Memory, processing system and methods for use therewith  
A memory includes a selected bitline coupled to the array of memory cells. A column voltage booster produces a boosted column enable signal. A column multiplexer passes a signal on the selected...
7301824 Method and apparatus for communication within an integrated circuit  
Method and apparatus for communication within an integrated circuit is described. In one example, an integrated circuit includes a first logic circuit, a second logic circuit, first...
7301798 Random access memory cell of reduced size and complexity  
A memory cell ( 1 ), includes a flip-flop ( 2 ) that has additional read/write terminals; a 1-bit write line (wb 11 ); a first transistor (T 4 ) switching between the 1-bit write line and the...
7292479 Memory device with multistage sense amplifier  
A memory device with a multistage sense amplifier is disclosed. According to one aspect, a memory device has a memory cell array having at least one memory cell, at least one sense amplifier....
7292498 Factored nanoscale multiplexer/demultiplexer circuit for interfacing nanowires with microscale and sub-microscale electronic devices  
Embodiments of the present invention are related to nanoscale multiplexers and demultiplexers that employ randomly fabricated interconnections between nanowire signal lines and microscale or...
7289379 Memory devices and methods of operation thereof using interdependent sense amplifier control  
A memory device includes a control circuit configured to disable a local input/output line sense amplifier responsive to a global input/output line sense amplifier enable signal. The device may...
7289373 High performance memory device  
A memory device is provided comprising a memory array consisting of a plurality of memory cells. These memory cells are accessed via a plurality of word lines and a plurality of bit lines....
7286415 Semiconductor memory devices having a dual port mode and methods of operating the same  
A memory device having a dual port function includes a memory cell array and a switching unit. The memory cell array has a first port and a second port. The switching unit assigns first data...
7286416 Non-volatile semiconductor memory device and semiconductor memory device  
For each memory block, a predecoder for predecoding an applied address signal, an address latch circuit for latching the output signal of the predecoder, and a decode circuit for decoding an output...
7280413 Nonvolatile semiconductor memory  
A transmission transistor transmitting a drain voltage is connected to an electrically rewritable nonvolatile memory cell. An operation control circuit controls program operation for increasing a...
7272056 Data output controller in semiconductor memory device and control method thereof  
A data output controller of a high-speed memory device and a method therefore. The data output controller includes a first section for detecting a unit delay multiple of an external clock signal...
7269089 Divisible true dual port memory system supporting simple dual port memory subsystems  
A random access memory circuit and a method for configuring the same. The circuit includes a first array of memory cells including a first plurality of ports and a second plurality of ports, and a...
7266020 Method and apparatus for address and data line usage in a multiple context programmable logic device  
A method and apparatus to provide triple modular redundancy (TMR) in one mode of operation, while providing multiple context selection during a second mode of operation. Intelligent voting...
7263011 Memory circuit with flexible bitline-related and/or wordline-related defect memory cell substitution  
The inventive memory circuit comprises a main memory block and a substitution memory block for substitution of defect memory cells, with the substitution memory block being external to the main...
7257036 Method and apparatus for storage device read phase auto-calibration  
The present invention provides a method and apparatus for performing read phase auto-calibration of a storage device. The method includes writing the data with at least one predetermined pattern...
7257013 Method for writing data into a memory cell of a conductive bridging random access memory, memory circuit and CBRAM memory circuit  
The present invention refers to a method for writing data into a memory cell of a conductive bridging random access memory and to a memory circuit comprising memory cells with programmable...
7251171 Semiconductor memory and system apparatus  
A register part of a mode register has a plurality of operation setting parts in which plural types of operating specifications are respectively set to operate the semiconductor memory. The mode...
7251715 Double data rate scheme for data output  
Systems, devices, and methods for a double data rate memory device includes a storage element, a first pipeline, and a second pipeline. The pipelines are connected to the storage unit to pass or...
7251180 Semiconductor memory device  
An apparatus a counter, storage units for storing count values interrupted by a row address whose refresh period is subject to change; comparator circuits for comparing the counter outputs and the...
7236421 Read-modify-write memory using read-or-write banks  
Minimal memory access times are realized by using a single access to a read-modify-write bank. read-modify-write memory including at least one read-or-write bank is operated in a manner that uses...
7230872 Efficent column redundancy techniques  
The present invention relates to a system and method adapted to increase memory cell and memory architecture design yield. The present invention includes memory architecture having a decoder and a...
7230865 Input/output line sharing apparatus of semiconductor memory device  
Provided is an input/output line sharing apparatus of a semiconductor memory device. In this apparatus, a global input/output line is shared by a data line signal and a test mode signal, and an...
7230856 High-speed multiplexer latch  
Embodiments of a high-speed multiplexer latch are described. The multiplexer latch may include a multiplexer and a latch coupled to each other at a first node and a second node. The multiplexer...
7225306 Efficient address generation for Forney's modular periodic interleavers  
An efficient way to generate the address sequence for the RAM implementation of Forney's (P, D, m) interleavers requires only A+1+2P memory locations, which is close to the theoretical minimum....
7221185 Method and apparatus for memory block initialization  
In one aspect of the invention, a circuit for generating addresses for memory initialization within a programmable logic device (PLD) is provided. The circuit includes input registers, which are...
7218569 Memory circuit, and method for reading out data contained in the memory circuit using shared command signals  
The present invention relates to a memory circuit having a memory cell array for storing data, and having a command decoding circuit for receiving command signals, and having a setting memory for...
7218558 Semiconductor memory devices having column redundancy circuits therein that support multiple memory blocks  
Semiconductor memory devices include a memory array having a plurality of multi-column memory blocks therein and a multi-column redundant memory block. A redundancy column selecting unit is...
7215580 Non-volatile memory control  
According to an embodiment of the present invention, there is provided a method and apparatus for use in a memory system having a non-volatile memory and a controller for limiting the number of...
7212448 Method and apparatus for multiple context and high reliability operation of programmable logic devices  
A method and apparatus to provide triple modular redundancy (TMR) in one mode of operation, while providing multiple context selection during a second mode of operation. Intelligent voting...
7209394 Memory structure for providing decreased leakage and bipolar current sensitivity  
A memory circuit. In one embodiment, the memory circuit includes a first one-hot multiplexer having a first plurality of local bitlines and a second one-hot multiplexer having a second plurality of...
7209393 Semiconductor memory device and method for multiplexing write data thereof  
A semiconductor memory device including a write multiplexer unit that multiplexes write data transmitted to a global I/O bus disposed in front of a write driver. The semiconductor memory device...
7203101 Semiconductor memory device and defect remedying method thereof  
A semiconductor memory device formed on a semiconductor chip comprises a plurality of first memory arrays, a plurality of second memory arrays, a first voltage generator, and a plurality of first...
7196940 Method and apparatus for a multiplexed address line driver  
A method and apparatus for multiplexing various voltage magnitudes onto the address line of a memory cell. An address line voltage generator applies complex analog voltage magnitudes to a memory...
7193874 Content addressable memory device  
A content addressable memory (CAM) device having a memory, a hash index generator to associate a search value with a unique location within a memory, and a compare circuit. The index generator...
7184322 Semiconductor memory device and control method thereof  
A semiconductor memory device has common terminals shared between a part or all of address terminals for receiving n bits of an address signal and data terminals for outputting a data signal with...
7184290 Logic process DRAM  
A dynamic random access memory (DRAM) unit includes pluralities of bit line pairs and word lines. Each bit line pair includes first and second bit lines aligned with each other in an end-to-end...
7170817 Access of two synchronous busses with asynchronous clocks to a synchronous single port ram  
A method and circuit are provided for controlling access of two synchronous busses with asynchronous clocks to a synchronous single port Random Access Memory (RAM). In one preferred method, the...
7167409 Semiconductor memory device  
A cell array in the semiconductor memory device is divided into two blocks. Each of control signal lines for transmission of control signals are also divided into a first portion and a second...
7164607 Dual bus memory burst architecture  
Methods and apparatus for a memory device including a burst architecture employ a double bus architecture that is multiplexed onto an output bus. The resulting architecture effectively facilitates...
7161844 Method and apparatus for compensating for bitline leakage current  
A bitline leakage current compensation circuit for compensating for leakage current in an operational memory array by measuring the leakage current in a non-operational memory array or a dummy...
7151699 Semiconductor memory device  
Provided is a semiconductor memory device, which is capable of further simplifying the data multiplexing structure on a data write path, thereby preventing a timing mismatch in data input from...
Matches 101 - 150 out of 865 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >