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7495979 |
Method and system for in-situ parametric SRAM diagnosis
This invention is about a system for diagnosing memory cells in a memory module. A first multiplexer module selectively connects a diagnosis signal in response to a multiplexer control signal to a...
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7486542 |
General purpose register circuit
A general purpose register circuit that stores and outputs desired data as required by a program stored in a storage device, has a memory cell which is connected to a word line and a bit line for...
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7477551 |
Systems and methods for reading data from a memory array
One embodiment of the present invention includes a column multiplexer for accessing data from a memory array comprising an output node having a logic state that is based on a logic state of a...
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7477565 |
Redundancy program circuit and methods thereof
A redundancy program circuit and methods thereof. The redundancy program circuit may include a master fuse circuit with a master fuse outputting an operation enable signal to indicate a master fuse...
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7474588 |
Data output circuits for an integrated circuit memory device in which data is output responsive to selective invocation of a plurality of clock signals, and methods of operating the same
A data output circuit for an integrated circuit memory device includes a control circuit that is configured to generate a plurality of clock signals responsive to at least a portion of a memory...
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7457172 |
Memory device and method having data path with multiple prefetch I/O configurations
A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the...
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7457187 |
Design structure for in-system redundant array repair in integrated circuits
A design structure for repairing an integrated circuit during operation of the integrated circuit. The integrated circuit comprising of a multitude of memory arrays and a fuse box holding control...
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7457143 |
Memory device with shared reference and method
A memory device has a first core memory array, a second core memory array, a third core memory array and a fourth core memory array, and a first common reference section for the first core memory...
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7457169 |
Flash with consistent latency for read operations
A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The memory device includes a pipelined...
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7450456 |
Temperature determination and communication for multiple devices of a memory module
The temperature for multiple devices of a memory module are determined. In one example a memory module includes a printed circuit board, a plurality of memory chips on the printed circuit board,...
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7450460 |
Voltage control circuit and semiconductor device
A voltage control circuit includes capacitors, first switches that are respectively provided to the capacitors and selectively couple the capacitors with a given node, and second switches that are...
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7447110 |
Integrated circuit devices having dual data rate (DDR) output circuits therein
A dual data rate (DDR) output circuit has first and second data paths therein that are asymmetric. The first data path is provided through a single-stage latch unit and the second data path is...
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7440335 |
Contention-free hierarchical bit line in embedded memory and method thereof
A memory includes a plurality of lower level bit lines, a higher level bit line, and bit line driving circuitry. The bit line driving circuitry includes a plurality of bit line inputs, each bit...
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7437500 |
Configurable high-speed memory interface subsystem
A core including a write logic IP block, a read logic IP block, a master delay IP block and an address and control IP block. The write logic IP block may be configured to communicate data from a...
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7433980 |
Memory of and circuit for rearranging the order of data in a memory having asymmetric input and output ports
Circuits and methods of rearranging the order of data in a memory having asymmetric input and output ports are disclosed. According to one embodiment, a method comprises steps of providing an input...
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7430137 |
Non-volatile memory cells in a field programmable gate array
A non-volatile memory cell comprises a first floating gate transistor having a source, a drain, and a gate electrically coupled to a row line. A second floating gate transistor has a source, a...
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7426144 |
Semiconductor storage device
A semiconductor storage device comprising: a transfer control circuit for prefetching data of a predetermined number of bits stored in a memory array in response to a read command, and transferring...
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7423917 |
Data readout circuit of memory cells, memory circuit and method of reading out data from memory cells
A data readout circuit of memory cells for reading out data from the memory cells includes a determination circuit ( 3 ) that reads out a plurality of data from multiplexed memory cells ( 5 )...
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7420869 |
Memory device, use thereof and method for synchronizing a data word
The invention includes a memory device with a register device to which an output of a multiplexer is connected. The input of the multiplexer is connected to a buffer store. In addition, the memory...
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7417888 |
Method and apparatus for resetable memory and design approach for same
A resetable memory is described that includes a memory without reset capability having a data output coupled to a first input of a first multiplexer. A second input of the first multiplexer has a...
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7414916 |
Using dedicated read output path to reduce unregistered read access time for FPGA embedded memory
A memory unit includes width decoding logic enabling data to be accessed in a memory array at different data widths. To improve memory access speed, the memory unit also includes dedicated read...
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7411844 |
Semiconductor memory device having a redundancy information memory directly connected to a redundancy control circuit
A semiconductor memory device (M) includes a memory array (MA) having a plurality of memory cells, a redundancy array (RA) having a plurality of memory cells, a non-volatile redundancy information...
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7411839 |
Data input circuit of semiconductor memory device and data input method thereof
A data input circuit of a semiconductor memory device and a data input operating method thereof, in which data input margin can be secured. The data input circuit includes a strobe buffer that...
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7408483 |
Apparatus and method of generating DBI signal in semiconductor memory apparatus
An apparatus for generating a DBI signal in a semiconductor memory apparatus includes a data switching detection unit that detects whether or not previous data is consistent with current data and...
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7405990 |
Method and apparatus for in-system redundant array repair on integrated circuits
Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays....
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7405980 |
Shared terminal memory interface
A memory architecture for a disk drive system in which Synchronous Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM) functions are provided on separate integrated circuits, and an...
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7403446 |
Single late-write for standard synchronous SRAMs
Synchronous SRAM may conform to Std. Sync or early-write at an external interface whilst providing late-write internally.
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7403439 |
Bitline leakage limiting with improved voltage regulation
Circuit arrangements and methods are provided for regulating and maintaining voltage on bitlines of a semiconductor memory device. According to one embodiment, first and second regulation devices...
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7400034 |
Semiconductor device
There is provided a large capacity memory such as a DRAM and an SDRAM n which bonding pads PS and PD are not located at the center, but are displaced from the center between memory array regions UL...
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7400548 |
Method for providing multiple reads/writes using a 2read/2write register file array
Reading a plurality of consecutive entries and writing a plurality of consecutive entries with only one read address and one write address using a 2Read/2Write register file is provided. In one...
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7400540 |
Programmable memory and access method for the same
A programmable memory includes N number of one-time programmable (OTP) memory rows, an output module, a judge module, and a write-in module. The output module receives all data of the OTP memory...
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RE40423 |
Multiport RAM with programmable data port configuration
A RAM with programmable data port configuration provides for programmable configuration of RAM data ports, and in the case of a multiport RAM, for independent programmable configuration of each...
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7394681 |
Column select multiplexer circuit for a domino random access memory array
A column select multiplexer circuit for a domino random access memory array including a plurality of column selector circuits for selecting a column from a plurality of columns of static random...
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7391643 |
Semiconductor memory device and writing method thereof
To provide a semiconductor memory device comprising a phase-change memory and having high compatibility with DRAM interface. The memory cell array 18 comprises a memory cell that includes a...
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RE40356 |
Large-capacity semiconductor memory with improved layout for sub-amplifiers to increase operational speed
A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and...
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7379383 |
Methods of DDR receiver read re-synchronization
A method for reading data is provided. The method includes generating two or more pulses from a first clock signal by which the data to be read is received, using each generated pulse to latch data...
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7379380 |
Low power multi-chip semiconductor memory device and chip enable method thereof
A multi-chip semiconductor device capable of selectively activating and deactivating the individual semiconductor chips of the device and a chip enable method thereof are provided. The individual...
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7376021 |
Data output circuit and method in DDR synchronous semiconductor device
Embodiments of the present invention include a data output circuit that can read data in parallel from a plurality of latches in a pipeline circuit. Even-numbered data and odd-numbered data are...
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7369448 |
Input circuit for memory device
An input circuit for a semiconductor memory device is disclosed. The input circuit controlling transmission paths for data having passed through a data input buffer by using a 1-clock shifted block...
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7366031 |
Memory arrangement and method for addressing a memory
A memory arrangement includes a plurality of switching elements arranged in the form of a binary tree. The memory elements are supplied with data to be stored by the switching elements coupled to...
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7362621 |
Register file with a selectable keeper circuit
A register file includes a multi-level multiplexer output circuit coupled to a global bit trace and keeper circuitry coupled to said global bit trace and a driving signal trace. The register file...
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7359252 |
Memory data bus structure and method of transferring information with plural memory banks
A data bus structure for a dynamic random access memory (DRAM) according to the present invention includes a series of data buses, each shared by a plurality of memory banks, and a switching device...
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7355899 |
Pipe latch circuit of multi-bit prefetch-type semiconductor memory device with improved structure
Provided is a pipe latch circuit of a multi-bit pre-fetch type semiconductor memory device with an advanced structure. The pipe latch circuit includes: a first latch circuit for simultaneously...
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7355881 |
Memory array with global bitline domino read/write scheme
A circuit for implementing memory arrays using a global bitline domino read/write scheme. The memory circuit includes a plurality of cells each configured to store a bit of data. The memory circuit...
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7352634 |
Nonvolatile latch circuit and system on chip with the same
A nonvolatile latch circuit and a system on a chip with the same feature detection of change of latch data in an active period to store new data in a latch without an additional data storage time....
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7353356 |
High speed, low current consumption FIFO circuit
A FIFO circuit includes a write counter circuit, a memory circuit, a read counter circuit and a selector circuit. The write counter circuit counts a write clock signal during a valid period of...
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7349233 |
Memory device with read data from different banks
In some embodiments, a chip includes at least four groups of memory banks and at least four groups of output conductors wherein each group of output conductors corresponds to a different one of the...
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7339810 |
Device and method for ensuring current consumption in search engine system
A search engine system ( 100 ) can include a key multiplexer ( 104 ) and logic circuit ( 108 ). A key from a previous operation can be received by logic circuit ( 108 ) and altered to generate an...
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7336554 |
Semiconductor memory device having a reduced number of pins
A semiconductor memory device includes an IO circuit for receiving or outputting command signals, address signals and data which are serialized and an IO signal control circuit for parallel...
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7333379 |
Balanced sense amplifier circuits with adjustable transistor body bias
Structures of balanced sense amplifier circuits and methods for operating the same. The structure comprises a reading circuit, which includes a first transistor and a second transistor. The first...
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