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5377143 Multiplexing sense amplifier having level shifter circuits  
A memory system comprising a memory array having at least two pairs of data lines, first and second data lines corresponding to columns in the memory array. The memory array also includes two level...
5377144 Memory array reconfiguration for testing  
A memory part (10), with memory (14) subarrays arranged in different ways, provides one data input and output path for normal operation and another data input and output path for test mode...
5373467 Solid state memory device capable of providing data signals on 2N data lines or N data lines  
A solid state peripheral storage device in compliance with the PCMCIA standard provides data signals on either 16 data signal lines or 8 data signal lines. The device has a plurality of even number...
5373470 Method and circuit for configuring I/O devices  
A method and circuit for configuring I/O devices, such as a DRAM or other memory device, uses master-slave buffer circuits in configurable I/O devices. When arranged in a master-slave arrangement,...
5365489 Dual port video random access memory with block write capability  
A dual port video random access memory device operates as a dual port by adding a serial access memory portion to a dynamic random access memory portion. A block write function can be selectively...
5361343 Microprocessor system including first and second nonvolatile memory arrays which may be simultaneously read and reprogrammed  
A microprocessor system includes a central processing unit (CPU) and a nonvolatile memory having a first memory array and a second memory array. A first address register is provided for storing a...
5361233 Semiconductor memory apparatus  
A semiconductor memory device is for randomly reading and writing data. Only a second bit line pair selected by a string selecting signal is amplified by a main amplifier. The number of the upper...
5359556 Semiconductor memories with serial sensing scheme  
Signals are simultaneously read out from a plurality of memory cells connected to one selected word line onto respective data lines. By successively making a selection out of data lines, signals...
5359717 Microprocessor arranged to access a non-multiplexed interface or a multiplexed peripheral interface  
A bus interface for use in a processing system of the type including a processor such as a microprocessor or a microcontroller permits the processor to access either a non-multiplexed peripheral...
5359557 Dual-port array with storage redundancy having a cross-write operation  
A method and system in a data processing system for providing a dual-port memory device having redundant data stored in multiple memory arrays. A first set of data and address latches, coupled to a...
5345573 High speed burst read address generation with high speed transfer  
A memory system coupled to a local bus of a microprocessor includes at least a pair of dynamic random access memories (DRAMs) and includes circuits for storing the first address of an address...
5343435 Use of a data register to effectively increase the efficiency of an on-chip write buffer  
Using a separate data register effectively increases the efficiency of an on-chip write buffer implemented as a FIFO structure. The separate register holds the output data during write cycles,...
5343426 Data formater/converter for use with solid-state disk memory using storage devices with defects  
A computer system includes a main memory that is able to make use of DRAM memory devices having a relatively high level of bad cells (hard faults). An EDC circuit is provided which uses...
5341335 Decimating filter  
A decimating memory includes a memory having addressable memory locations. The memory forms a plurality of registers, each of the registers including at least one addressable memory location. The...
5341488 N-word read/write access achieving double bandwidth without increasing the width of external data I/O bus  
An N-word write access memory is described. Using a variation of conventional control signals RAS, CAS, WE and OE, an innovative scheme of signal protocol allows the N-bit word write memory to have...
5335202 Verifying dynamic memory refresh  
A dynamic memory having self refreshing capability performed without external strobing, is interruptable and can be strobed to initiate a refresh cycle for testing interrupt response timing. In...
5331600 Non-volatile programmable read only memory device having write-in unit sequentially writing data bits into memory cells for programming  
An electrically programmable read only memory device is equipped with a plurality of write-in circuits for concurrently writing a plurality of data bits into memory cells, wherein a write-in...
5323347 Semiconductor memory device storing two types of binary number data and method of operating the same  
A semiconductor memory device 1 includes a plurality of memory circuits 10. Each of the memory circuits 10 includes a data bit memory cell 11, a sign bit memory cell 12, a converting circuit 13 and...
5321652 Microcomputer having a dual port memory of supplying write data directly to an output  
A single chip microcomputer includes a multiport memory, such as a dual-port memory, having a data selector by which, when addresses which are input to first and second ports of the dual port...
5321651 Read and write circuitry for a memory  
A memory is provided with at least one temporary store and write abort circuitry having a control signal store and gating circuitry responsive to an output from the control signal store. Write...
5315178 IC which can be used as a programmable logic cell array or as a register file  
A programmable logic cell array (PLCA) architecture that provides efficient support for demultiplexers or multi-ported register files without sacrificing PLCA functionality or flexibility is...
5315553 Memory circuit test system using separate ROM having test values stored therein  
A memory test method and system are described which comprises a first memory array and a second memory array coupled to a plurality of row address lines within a memory system. During the testing...
5311519 Multiplexer  
A multiplexer circuit which is built up from a series of smaller submultiplexers (241-247, 251-254). It selects a number of adjacent bits, bytes or words from one register and places them in the...
5311468 Random access memory with a serial register arranged for quick access of a second bit from an arbitrary address  
A random access memory includes a memory array of storage cells arranged in addressable rows and columns. A serial register is coupled to the memory array and to a serial register address decoder....
5307321 Semiconductor memory device with particular bank selector means  
A semiconductor memory device has an aligner for aligning data. The aligner is disposed in front of a sense amplifier to directly receive data from an internal bus of a memory. This arrangement...
5307323 Dual-port memory  
A dual-port memory requiring fewer serial input/output pins. A multiplex/distribution circuit multiplexes data for n rows read from a memory cell array into m (m<n) pieces of serial data and...
5305319 FIFO for coupling asynchronous channels  
An efficient and optimized FIFO memory for use in a bus master system utilizes a multiplexing clock from which control signal defining bus cycles on asynchronous system and local buses. The FIFO...
5301155 Multiblock semiconduction storage device including simultaneous operation of a plurality of block defect determination circuits  
A semiconductor storage device including a plurality of blocks each having an array of memory cells includes an exclusive OR circuit provided in each of the plurality of blocks for making a...
5297086 Method for initializing redundant circuitry  
A method for initilizing redundant circuitry of a semiconductor memory device is disclosed. The method comprises sectioning the redundant circuitry and applying an initilizing pulse to each section...
5293332 Semiconductor memory device with switchable sense amps  
A semiconductor memory device, in which based on a write and non-write states of a memory transistor, a signal corresponding to a page mode and a normal mode is generated, and a switch circuit...
5293562 Device with multiplexed and non-multiplexed address and data I/O capability  
An electronic device receives data from an EEPROM by sending address information to it on one set of leads and receiving data back from it through a different set of multiplexed address/data leads....
5289413 Dynamic semiconductor memory device with high-speed serial-accessing column decoder  
A MOS memory device includes an array of rows and columns of memory cells, word lines connected to the rows of memory cells, and a plurality of pairs of bits lines connected to the columns. Sense...
5287310 Memory with I/O mappable redundant columns  
A byte-wide memory has a plurality of redundant columns. Each redundant column is capable of being mapped to any one of a plurality of input buffers and output buffers in place of a defective...
5285421 Scheme for eliminating page boundary limitation on initial access of a serial contiguous access memory  
In accordance with the present invention, a memory system capable of indefinite sequential access to a contiguous address space without stutter is provided. The memory system has a memory array...
5280449 Data memory and method of reading a data memory  
A data memory and a method of reading a data memory are described. Data words (Word0, Word1, Word2, Word3) are stored within the data memory within an array of memory cells arranged in columns and...
5280448 Dynamic memory with group bit lines and associated bit line group selector  
A dynamic type memory used as a video memory achieves high speed access operations, reduction of occupying area of the memory, and a stablization of data holding (retention) characteristics,...
5280601 Buffer memory control system for a magnetic disc controller  
A method for temporarily storing and retrieving 8-bit character information data for a magnetic disk information storage system in a number of 4×n DRAM buffer memory configurations. A virtual...
5278801 Flexible addressing for drams  
A memory controller for controlling access to a memory includes a mapper for mapping a physical address to a row address and a column address that are suitable for addressing first and second...
5276641 Hybrid open folded sense amplifier architecture for a memory device  
A hybrid open/folded bit line sense amplifier arrangement and accompanying circuitry primarily for use on a ULSI DRAM memory chip to reduce the area needed for a memory cell and eliminate noise...
5276650 Memory array size reduction  
An apparatus and method for reducing the size of memory arrays which are comprised of memory cells which use bit lines to access the cells. Adjacent cells in a row are assigned different word lines...
5274602 Large capacity solid-state memory  
A large capacity, solid-state memory device is disclosed in which information is stored in a plurality of large-area arrays of memory cells, each of which is a crossed-wire matrix of memory cells...
5270973 Video random access memory having a split register and a multiplexer  
A video random access memory includes memory cells arranged in rows and columns. The columns of memory cells are divided into first and second portions, and the cells of each row of the first...
5265054 Semiconductor memory with precharged redundancy multiplexing  
An integrated circuit memory is disclosed which includes redundant columns associated with a sub-array, and in which multiple input/output terminals are placed in communication with multiple...
5262990 Memory device having selectable number of output pins  
A memory device includes a memory array and a plurality of output pins. A control input is provided for receiving a control signal. The control signal can be in a first voltage state and a second...
5261068 Dual path memory retrieval system for an interleaved dynamic RAM memory unit  
A digital computer having a dual path memory retrieval system for a dynamic RAM memory unit comprised of any number of interleaved memory banks. The system includes means for asserting and...
5260902 Efficient redundancy method for RAM circuit  
A redundancy system for a random access memory circuit includes a plurality of groups, each having first and second multiplexers on opposite sides thereof, each group being made up of two squads...
5258951 Memory having output buffer enable by level comparison and method therefor  
A memory (20) has a read cycle and a write cycle. During the read cycle, differential data signals, corresponding to data provided by a selected memory cell, are superimposed on a first common mode...
5253203 Subarray architecture with partial address translation  
The physical organization of a memory cell array in an integrated circuit cache memory system is different from its logical organization because the bit lines of the array are divided into segments...
5233558 Semiconductor memory device capable of directly reading the potential of bit lines  
Memory cell arrays containing dynamic memory cells and write/read circuits for these memory cell arrays are arranged alternately. In the write/read circuit, read amplifiers are provided at a rate...
5231495 Digital signal processing device to execute time-sharing multiplex or separation of a plurality of kinds of digital signals  
By providing a mediator for selectively permitting an access request of a first processing circuit for processing a first digital signal to a memory and an access request of a second processing...
Matches 701 - 750 out of 865 < 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 >