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5661692 Read/write dual port memory having an on-chip input data register  
A dual-port memory having an on-chip color register for storage of input data for use in multiple write cycles is disclosed. The color register is written to during a special cycle, which is...
5659580 Data interleaver for use with mobile communication systems and having a contiguous counter and an address twister  
The present invention includes a data buffer, a contiguous counter and an address twister. The contiguous counter generates a contiguous sequence of addresses which are used to load data into the...
5654916 Semiconductor memory device having an improved sense amplifier arrangement  
A semiconductor memory device in which a plurality of data lines of a memory array comprising storage transistors arranged in a matrix form as those having a high or low threshold voltage according...
5649148 Fast digital signal processor interface using data interchanging between two memory banks  
A digital signal processor (DSP) interface comprised of a memory containing a pair of memory banks, apparatus for storing an input signal in a first one of the memory banks, apparatus for storing a...
5640361 Memory architecture  
A memory architecture for providing wide data words up to the width of the address word, or wider than the address word, without requiring separate groups of electrical contacts for data and...
5625603 Integrated circuit with unequally-sized, paired memory coupled to odd number of input/output pads  
An integrated circuit with an integer odd number C of electrical contacts, wherein each of the electrical contacts is for communicating a data value. The integrated circuit also includes four...
5621881 DRAM control device of a CD graphics decoder  
A DRAM control device of a CD graphics decoder for reading and writing font data on a DRAM, which is made simple for fabricating the ASIC, allowing it made smaller permitting it applied to a...
5621694 Semiconductor integrated device with an improved performance  
A semiconductor integrated circuit, which can process n-bit (n is an integer, n>1) instructions or data at a time, has queues for storing instructions or data of m (m>1) times n bits received...
5621696 Virtual multiple-read port memory array  
Multiple reads are made from an array of single-read port memory cells. An array of single-read port memory cells is provided with "steering" devices located between a column of cells and the...
5621695 SRAM with simplified architecture for use with pipelined data  
A high speed high capacity SRAM having a density of 256K bits or larger. Individual complementary memory cell pairs are arranged in memory blocks and are directly accessed during write and read...
5619455 Pipeline-operating type memory system capable of reading data from a memory array having data width larger than the output data width  
A pipeline-operating type memory system is arranged to have a first input unit for receiving a selector address signal for selecting data; a second input unit for receiving at least an address...
5619463 Integrated circuit device and test method therefor  
An integrated circuit device includes an oscillator; a counter; a switch for selectively connecting the oscillator to the counter in a test mode; and an output circuit for providing the output...
5608678 Column redundancy of a multiple block memory architecture  
According to the present invention, column redundancy circuitry provides column redundancy to an integrated circuit memory device having a multiple block memory architecture with limited...
5604701 Initializing a read pipeline of a non-volatile sequential memory device  
A sequential memory device having a read pipeline data structure for reading data from a bitline of a memory array of the device is disclosed. The read pipeline data structure includes at least one...
5602780 Serial to parallel and parallel to serial architecture for a RAM based FIFO memory  
A FIFO memory (4) provides serial to parallel and parallel to serial data conversion. A read frame buffer (40) and a write frame buffer (30) are coupled with a RAM array (22). Serial input data is...
5596740 Interleaved memory conflict resolution with accesses of variable bank widths and partial return of non-conflicting banks  
A shared interleaved memory having a relatively large number of banks employs circuitry and methodology for resolving bank conflicts without significantly inducing delay into the data path. A first...
5596533 Method and apparatus for reading/writing data from/into semiconductor memory device  
A method and an apparatus for reading/writing data from/into a semiconductor memory device. In a read mode, a memory cell array block from which data is to be read is selected in response to a row...
5590083 Process of writing data from a data processor to a memory device register that is separate from the array  
A dual-port memory having an on-chip color register for storage of input data for use in multiple write cycles is disclosed. The color register is written to during a special cycle, which is...
5587960 Integrated circuit memory device with voltage boost  
An integrated circuit memory device is provided with a voltage boost facility. The voltage boost facility is used with a so-called divided wordline architecture, in which a wordline is divided into...
5586078 Dynamic type memory  
A DRAM includes memory blocks in a form of division of shared sense amplifier configuration in which sub arrays and sense amplifiers serving as cache memories are alternately arranged in the X...
5579263 Post-fabrication selectable registered and non-registered memory  
A memory and a method involving the memory. The memory includes a memory array having a data quantity output for outputting a data quantity and a data output driver having an input for receiving...
5579277 System and method for interleaving memory banks  
A device and method are provided for mapping address bus bits to memory address by using interleaved and non-interleaved modes so that every desired row and column configuration stored in a...
5572691 Apparatus and method for providing multiple data streams from stored data using dual memory buffers  
An apparatus and method are disclosed for processing successive frames of data to provide a plurality of data streams containing the data in different orders. In an illustrated embodiment, two...
5572477 Video ram method for outputting serial data  
The present invention relates to a video RAM as a dual port memory, and more particularly to the video RAM which is adjustable to a high speed system clock and a serial data output method thereof....
5572467 Address comparison in an inteagrated circuit memory having shared read global data lines  
A synchronous integrated circuit memory (30) has read global data lines shared between data read from a memory array (32) and data read from a data-in register (40) during a read-after-write. A...
5570320 Dual bank memory system with output multiplexing and methods using the same  
A memory circuit 300 is provided which includes first and second banks 201a and 201b of memory cells arranged in rows and columns. Row decoder circuitry 210 is provided for selecting a row in at...
5568443 Combination dual-port random access memory and multiple first-in-first-out (FIFO) buffer memories  
A data processor memory system that combines in a single memory array, a plurality of first-in-first-out (FIFO) buffer memories and a dual-port random access read-write memory (RAM). The memory...
5568427 Memory and method of reading out of the memory  
A memory and a method for reading out of memory including a register for holding one row of data of a memory cell array, a plurality of first switching transistors for switching ON/OFF between a...
5568442 RISC processor having improved instruction fetching capability and utilizing address bit predecoding for a segmented cache memory  
A RISC processor utilizes a segmented cache to reduce word line loading to reduce power consumption and increase speed. Address bit are predecoded to activate a selected segment. Groups of...
5568432 Semiconductor memory device including redundancy memory cell remedying defective memory cell  
A sense amplifier portion provides a predetermined number of data among a plurality of data provided from a bit line pair to a multiplexer. A sense amplifier amplifies data provided from a...
5563827 Wordline driver for flash PLD  
A wordline driver for a wordline in an integrated programmable logic device (PLD) having flash memory cells. The wordline driver includes an input terminal that accepts a binary wordline input...
5563830 Semiconductor memory device with data bus having plurality of I/O pins and with circuitry having latching and multiplexing function  
The semiconductor memory device disclosed includes a data bus, an I/O terminal, a distributing circuit, a multiplexer circuit, and a latching circuit. The data bus includes a plurality of I/O pins....
5561630 Data sense circuit for dynamic random access memories  
An improved data sense for a DRAM. Each bit line pair is coupled through a pair of high-resistance pass gates to a sense amp. During sense, the high-resistance pass gates act in conjunction with...
5557575 Look ahead flag for FIFO  
The invention provides fast generation of flag signals for devices such as a first-in first-out buffers by looking ahead and predetermining flag signals for future possible states of the device....
5550774 Memory cache with low power consumption and method of operation  
A memory cache (46) has a plurality of tag arrays (20, 22, 24, 26), a plurality of comparators (38, 40, 42, 44), a plurality a data arrays (12, 14, 16, 18), and a plurality of sense amplifiers (48,...
5548553 Method and apparatus for providing high-speed column redundancy  
A semiconductor memory device according to the invention includes a main memory array comprising a plurality of memory sub-arrays. Each of the memory sub-arrays comprises a plurality of columns and...
5546343 Method and apparatus for a single instruction operating multiple processors on a memory chip  
A random access memory chip is comprised of static random access storage elements, word lines, and bit lines connected to the storage elements, a sense amplifier connected to each of the bit lines,...
5544104 Virtual crosspoint memory  
An interconnection-point memory which includes an array of N1 input buses (Rj) intended to be connected to a first plurality of N1 data-sender devices, an array of N2 output buses (Ck) intended to...
5544101 Memory device having a latching multiplexer and a multiplexer block therefor  
A memory device (10) is provided which includes a memory array (12), a multiplexer block (14) and a control block (16). The memory array (12) is operable to provide a plurality of memory array...
5544293 Buffer storage system and method using page designating address and intra-page address and detecting valid data  
A buffer storage system and method using a page designating address and an intra-page address for information processing according to a logical address is provided. The buffer storage system...
5542063 Digital data processing system with facility for changing individual bits  
A system for changing bits of a byte unit individually comprises a data processing unit including specifying circuitry for specifying bit selection information indicative of a predetermined bit in...
5537355 Scheme to test/repair multiple large RAM blocks  
The method and apparatus of the present invention provides an interface between a testing device and a random access memory (RAM). The RAM comprises two types of RAM, a TAG RAM and a data RAM. In...
5537351 Semiconductor memory device carrying out input and output of data in a predetermined bit organization  
In a general read out operation, data read out from a memory cell array is amplified by a preamplifier group. The amplified data is provided to a selector unit. The selector unit responds to a bit...
5537352 Integrated semiconductor memory configuration  
An integrated semiconductor memory configuration includes a memory region having a plurality of segments. Each of the memory region segments have a plurality of read amplifiers and bit lines. Each...
5535172 Dual-port random access memory having reduced architecture  
A dual-port semiconductor memory device is disclosed that includes a number of array blocks (12) having memory cells disposed in rows and local columns, with each local column having a local bit...
5530836 Method and apparatus for multiple memory bank selection  
In one aspect a memory bank selection system includes two asynchronous RAS pins and a single CAS pin, a switching circuit for each memory bank and a bank address decoder with an output to each...
5530824 Address translation circuit  
A CAM/SRAM structure (42) performs address translations of variable length blocks, a "block address translator." Each address translation is stored in a register broken into an upper half and a...
5528551 Read/write memory with plural memory cell write capability at a selected row address  
A read/write memory for use with a central processing unit is disclosed, which has the capability of writing the same data state to multiple memory cells in a selected row in a single cycle. The...
5526307 Flash EPROM integrated circuit architecture  
Contactless flash EPROM cell and array designs, and methods for fabricating the same result in a dense, segmentable flash EPROM chip. The flash EPROM cell is based on a drain-source-drain...
5521879 Synchronous dynamic random acess memory  
A synchronous dynamic random-access memory has transparent latch circuits that latch address signals in synchronization with a clock signal. An X-address is latched following activation of a first...
Matches 601 - 650 out of 866 < 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 >