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5870340 |
Multiplexer
A semiconductor integrated circuit device has a data selecting circuit connected to a first power supply terminal, a precharge circuit, connected to a second power supply terminal, for receiving a...
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5860092 |
Apparatus and method for addressing a cache memory in a computer system utilizing cache tag memory with integrated adder and pre-decode circuit
A tag memory circuit includes an address index input, an address offset input and an integrated adder and pre-decode circuit. The integrated adder and pre-decode circuit has a first addend input...
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5859795 |
Multi-level memory circuits and corresponding reading and writing methods
The present invention relates to a memory circuit of the multi-level type, i.e. a memory circuit having a plurality of memory elements, each adapted to store more than one binary information unit,...
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5856947 |
Integrated DRAM with high speed interleaving
An integrated circuit includes a controller and a memory to implement a graphics controller. The controller and memory are controlled by a common clock signal to operate synchronously with each...
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5844844 |
FPGA memory element programmably triggered on both clock edges
A programmable memory element clocks in new data on both rising and falling edges of the clock, thereby optionally operating at twice the frequency of the distributed clock. The circuit according...
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5838624 |
Circuits for improving the reliability of antifuses in integrated circuits
A circuit improves the reliability of antifuses in certain types of systems by substantially eliminating the continuous undesirable applications of voltages across antifuse terminals. To accomplish...
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5836007 |
Methods and systems for improving memory component size and access speed including splitting bit lines and alternate pre-charge/access cycles
A memory system having split logical bit lines and interleaved pre-charge/access cycles is provided. A bit line access circuit supports multiple conductors per logical bit line and pre-charges the...
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5835421 |
Method and apparatus for reducing failures due to bit line coupling and reducing power consumption in a memory
A method and apparatus for reducing failures due to bit line coupling and reducing power consumption in a memory (10). The method comprises precharging a first group of bitlines (22) to a first...
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5835956 |
Synchronous dram having a plurality of latency modes
A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit...
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5835431 |
Method and apparatus for wafer test of redundant circuitry
A method and apparatus for testing redundant circuitry within a memory array is provided. A control unit is described to interface a memory array to a wafer tester to selectively enable redundant...
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5831929 |
Memory device with staggered data paths
A memory device includes input and output data sequencers that transfer data between a memory array and a data bus where transfers between the data sequencers and the data bus are controlled by a...
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5831915 |
Memory device with clocked column redundancy
A semiconductor memory device including: at least one output data terminal; a matrix of memory cells having a plurality of columns of memory cells; multiplexer circuitry associated with the matrix...
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5831889 |
Cache memory device and manufacturing method thereof
A method is for manufacturing a cache memory device for writing cache data into and reading cache data from a storing region of a memory cell array designated according to a portion of an address...
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5829016 |
Memory system with multiplexed input-output port and systems and methods using the same
A memory including a plurality of input/output terminals 220 for exchanging data bits during a data access cycle and receiving command and control bits during a command and control cycle. The...
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5828610 |
Low power memory including selective precharge circuit
A low power RAM device including a bit line precharge circuit which selectively precharges only those bit lines which will be read in an effort to minimize precharge and overall RAM power...
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5829015 |
Semiconductor integrated circuit device having multi-port RAM memory with random logic portion which can be tested without additional test circuitry
Multi-port RAM having a RAM core and signal transfer circuit transforming a predetermined signal between the RAM core and a random logic portion. The signal transfer circuit includes a scan path...
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5825712 |
Semiconductor integrated circuit
The present invention intends to provide a semiconductor device integrated circuit having an additive circuit capable of the evaluation of the dynamic performance of a memory block in a mixed logic...
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5822257 |
Semiconductor memory device capable of relieving fixed-failure memory cells and refresh-failure memory cells
A memory device has a plurality of word lines, a plurality of bit lines crossing the word lines, and a memory cell array having memory cells disposed at respective points of intersection between...
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5815432 |
Single-ended read, dual-ended write SCRAM cell
A static random-access memory (SRAM) cell with one or more storage elements connected to a sensing component by a single transmission line. Each storage element is connected to the transmission...
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5805520 |
Integrated circuit address reconfigurability
An integrated circuit having an internal switch including remap-multiplexers that are actuated through either hardware or firmware for remapping external addresses such that the IC switches between...
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5793683 |
Wordline and bitline redundancy with no performance penalty
Wordline and bitline redundancy is provided in large memory arrays but without the performance penalty normally associated with the redundancy calculation. All redundant elements are placed in a...
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5790462 |
Redundancy control
An integrated circuit memory structure is disclosed where the read and write buses (true and complement) are coupled to redundant input/output select circuits through permanently programmable...
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5790454 |
Data sensing apparatus and method of multi-bit memory cell
A data sensing apparatus and method of a multi-bit memory cell includes a first step of generating 2 m -1 different reference voltages, a second step of applying a first intermediate reference...
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5787454 |
Recorder buffer with interleaving mechanism for accessing a multi-parted circular memory array
A buffer comprises a memory array, a write circuit and a read circuit. The memory array comprises one or more memory banks. Each of the memory banks is made up of a plurality of memory cells. Each...
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5787041 |
System and method for improving a random access memory (RAM)
An improved random access memory (RAM) system enhances the speed and reduces power dissipation and logic complexity associated with a RAM. The RAM system includes first and second pluralities of...
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5787310 |
Microcomputer
A microcomputer which comprises a processor and a memory integrated on one chip wherein the memory is arranged in a plurality of memory cell region rows, and a processor is arranged between the...
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5777941 |
Column multiplexer
A column select multiplexer for a memory array organized in modules, each module handling two sets or bunches each of a certain minimum number of bitline, is realized in a space opposite to the...
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5761129 |
Method and apparatus for I/O multiplexing of RAM bus
A RAM and I/O controller is provided with logic for controlling access to a DRAM and to one or more input and/or output latches, each of which are coupled to a RAM data bus. The logic receives...
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5757690 |
Embedded ROM with RAM valid bits for fetching ROM-code updates from external memory
An embedded ROM has a column of static RAM cells attached to the end of the row lines. When a row of ROM cells is activated by the row line, a RAM cell is also activated by the row line. The RAM...
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5757704 |
Semiconductor memory integrated circuit with simplified circuit structure
In a semiconductor memory device, an first address register stores an inputted address and a second address register stores a write address for a write data. A comparing circuit compares both of...
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5754010 |
Memory circuit and method for sensing data
A memory circuit (24) includes a sense amp circuit (30) that uses multiplexers (86) in a column mux (32) for pre-charging only selected bitlines in order to limit the current during a read...
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5748561 |
Semiconductor memory device with fast successive read operation
A semiconductor memory device of the invention includes a memory cell array having a plurality of memory cells, row selector for selecting a row of the memory cell array corresponding to a row...
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5745421 |
Method and apparatus for self-timed precharge of bit lines in a memory
A method and apparatus are disclosed for self-timing the precharge of bit lines (22) in a memory array. A reference column bit line (26) is charged to create a reference column voltage. The bit...
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5734615 |
Memory testing apparatus for microelectronic integrated circuit
A testing apparatus is integrally formed on a microelectronic integrated circuit chip for testing a plurality of memories including parallel outputs having a total of a first number of bits. The...
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5719810 |
Semiconductor memory device having cache memory function
A semiconductor memory device comprising a memory cell array for storing input data therein, a data output buffer for outputting the data stored in the memory cell array externally, an output...
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5717645 |
Random access memory with fast, compact sensing and selection architecture
A random access memory (RAM) (10) is disclosed. A network of driver lines (28) extends over a number of core arrays (12a-12p) connecting a control bank 24 with column decode banks (26a and 26b),...
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5715201 |
Self-tracking delay-matching write pulse control circuit and method
A self-tracking write pulse control circuit to determine the time provided to complete a write operation to a memory. A tracking array including at least a first tracking memory cell configured on...
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5708615 |
Semiconductor memory device with reduced current consumption during precharge and reading periods
A semiconductor memory device with low current consumption is disclosed. A bit line selecting circuit (3) establishes electrical connection between a bit line (BL) selected during a read period and...
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5699530 |
Circular RAM-based first-in/first-out buffer employing interleaved storage locations and cross pointers
The first-in/first-out (FIFO) buffer includes a first bank of individual storage elements for storing even data and a second bank of individual storage locations for storing odd data. Precharge...
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5689680 |
Cache memory system and method for accessing a coincident cache with a bit-sliced architecture
A "bit-sliced" construction cache module dictates dual TAG RAM Structures and dual invalidation queues, yielding enhanced performance: putting half the TAG array in each of two cache arrays, and...
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5689731 |
Programmable serializer using multiplexer and programmable address counter for providing flexiblity in scanning sequences and width of data
A programmable serializer comprising a multi-bit input port, a multi-bit output port, at least one multiplexer and at least one programmable address counter corresponding to the multiplexer for...
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5689462 |
Parallel output buffers in memory circuits
A memory circuit with programmable memory array organization and number of data output terminals, capable of connecting unused output buffers in parallel in organizations requiring fewer output...
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5684973 |
Expandable memory system and method for interleaving addresses among memory banks of different speeds and sizes
An expandable memory system and a method for operating a memory system having a variable number of memory banks are described. The memory system can utilize a variable number of separately...
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5680504 |
Apparatus and method for storing and reproducing digital data
In the prior art, DRAMs (Dynamic Random Access Memories) are used to store and reproduce digital data, or ARAMs (Audio Random Access Memories) are used to store and reproduce speech. The components...
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5680360 |
Circuits for improving the reliablity of antifuses in integrated circuits
A circuit improves the reliability of antifuses in certain types of systems by substantially eliminating the continuous undesirable applications of voltages across antifuse terminals. To accomplish...
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5677877 |
Integrated circuit chips with multiplexed input/output pads and methods of operating same
Integrated circuit chips with multiplexed input/output pads include means for expanding the functional and diagnostic capability of the circuit by increasing the effective number of input/output...
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5673227 |
Integrated circuit memory with multiplexed redundant column data path
An integrated circuit memory (10) has a redundant column (20) located approximately in the middle a memory array (80, 81). Input/output (I/O) blocks (49, 70) are located on a periphery of the...
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5668767 |
Polled FIFO flags
A First-In-First-Out (FIFO) memory device having polled status flags to provide the status of the FIFO memory device when requested by an external source. The write pointer and the read pointer in...
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5666312 |
Column redundancy scheme for a random access memory incorporating multiplexers and demultiplexers for replacing defective columns in any memory array
The present invention relates to methods and apparatus for mapping spare columns to defective columns in a fabricated random access memory (RAM). The defective columns correspond to improperly...
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5663922 |
Method for the anticipated reading of serial access memory, and memory pertaining thereto
A method and apparatus for reading a memory, such that the address decoding is started when the address bits have not yet all been received. All the information elements corresponding to the...
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