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7602634 Dynamic RAM storage techniques  
Dynamic RAM (DRAM) cells are provided. Data can be read from a DRAM cell without draining the stored charge stored in the cell. During a read cycle, current flows between a Read Bit line and a...
7532496 System and method for providing a low voltage low power EPROM based on gate oxide breakdown  
A system and method are disclosed for providing an electrically programmable read only memory (EPROM) in which each memory cell comprises an NMOS select transistor and a PMOS program transistor...
7277316 Dynamic RAM storage techniques  
Dynamic RAM (DRAM) cells are provided. Data can be read from a DRAM cell without draining the stored charge stored in the cell. During a read cycle, current flows between a Read Bit line and a...
7245525 Data restore in thryistor based memory devices  
In a thyristor based memory cell, one end of a reversed-biased diode is connected to the cathode of the thyristor. During standby, the second end of the diode is biased at a voltage that is higher...
7239558 Method of hot electron injection programming of a non-volatile memory (NVM) cell array in a single cycle  
A non-volatile memory (NVM) cell splits its basic functions, i.e. program, erase, read and control, among a four PMOS transistor structure, allowing independent optimization of each cell function....
7221580 Memory gain cell  
A memory cell includes: a charge storage element (e.g., capacitor); a switch constructed and arranged to selectively connect the charge storage element to a first data line, responsive to a first...
7149940 Device and method for reading data stored in a semiconductor device having multilevel memory cells  
A semiconductor device has multilevel memory cells, each cell storing at least three levels of data each. The multilevel memory cells are arranged so as to correspond to a physical address space,...
7027326 3T1D memory cells using gated diodes and methods of use thereof  
A memory cell comprises: (1) a write switch, the first terminal of the write switch coupled to an at least one bitline, the control terminal of the write switch coupled to the first control line;...
7016246 Three-transistor refresh-free pipelined dynamic random access memory  
A memory includes first circuit RFPDRAM including memory cells and operating in response to first clock signal, second circuit and third circuit coupled with first circuit and bus coupling first...
7002874 Dual word line mode for DRAMs  
An integrated circuit memory includes circuitry for individually activating word lines in a first one memory cell per bit operational mode, simultaneously activating at least two word lines in a...
6982897 Nondestructive read, two-switch, single-charge-storage device RAM devices  
A random access memory (RAM) circuit is coupled to a write control line, a read control line, and one or more bitlines, and includes a write switch having a control terminal and first and second...
6912151 Negative differential resistance (NDR) based memory device with reduced body effects  
A memory device (such as an SRAM) using negative differential resistance (NDR) elements is disclosed. Body effect performances for NDR FETs (and other FETs) that may be used in such device are...
6862205 Semiconductor memory device  
The semiconductor memory device includes: a memory cell including a capacitor having a charge storage node and a first MIS transistor and a second MIS transistor each having a source connected to...
6847548 Memory with multiple state cells and sensing method  
A memory has an array made up of transistors that have two charge storage regions between the channel and control gate. Each bit is made up of two charge storage regions that are from different...
6768668 Converting volatile memory to non-volatile memory  
The invention relates to a method for converting volatile memory cells to non-volatile memory cells with minimal modifications. There is included a volatile memory cell which is modified to...
6707697 FAMOS type non-volatile memory  
An FAMOS memory includes memory cells, with each memory cell including an insulated gate transistor, and a first access transistor having a drain connected to a source of the insulated gate...
6680864 Method for reading a vertical gain cell and array for a dynamic random access memory  
A vertical gain memory cell including an n-channel metal-oxide semiconductor field-effect transistor (MOSFET) and p-channel junction field-effect transistor (JFET) transistors formed in a vertical...
6678198 Pseudo differential sensing method and apparatus for DRAM cell  
Present invention describes an efficient implementation of differential sensing in single ended DRAM arrays. According to one embodiment of the present invention, a respective local sense amplifier...
6671210 Three-transistor pipelined dynamic random access memory  
A semiconductor device includes a plurality of DRAM memory cells each having first, second, and third MOS transistors; a plurality of first word lines coupled to the gates of the first MOS...
6628551 Reducing leakage current in memory cells  
A memory cell having first and second access transistors coupled to a storage transistor is disclosed. The access transistors are high gate threshold voltage transistors to reduce leakage current...
6614696 Semiconductor device having memory cells coupled to read and write data lines  
A semiconductor integrated circuit is disclosed, in which a memory is activated at high speed in commensurate with a high-speed logic circuit mounted with the memory in order to reduce the cost...
6600677 Memory circuit capable of simultaneous writing and refreshing on the same column and a memory cell for application in the same  
A system-on-chip (SOC) device or a random access memory (RAM) chip includes a RAM block. The RAM block includes memory cells, each of which has three transistors. Each memory cell is coupled to...
6466474 Memory module having a two-transistor memory cell  
A memory module stores digital data. The memory module has many memory cells biased by a voltage source. Each memory cell has an access transistor electrically connected to a word line and a bit...
6400612 Memory based on a four-transistor storage cell  
A memory organized as a two-dimensional array of data storage cells having a plurality of rows and columns. Each data storage cell has first, second, third, and fourth terminals, each data storage...
6392488 Dual oxide gate device and method for providing the same  
An RF power amplifier is provided for use with wireless transmission systems such as cellular phones. An RF power amplifier includes direct drive amplifier circuitry operating in a push-pull...
6317365 Semiconductor memory cell  
A semiconductor memory cell is configured using a sense amplifier and a memory cell containing MOS transistors. In a write cycle, the sense amplifier inputs write data to accumulate charges in the...
6314017 Semiconductor memory device  
A semiconductor memory device comprising a write transistor with a gate connected to a write word line and with a first impurity region forming a source or drain connected to a bit line, a read...
6307788 Semiconductor memory cell having read/write circuit capable of performing random access  
A semiconductor memory cell is configured using a sense amplifier and a memory cell containing MOS transistors. In a write cycle, the sense amplifier inputs write data to accumulate charges in the...
6266269 Three terminal non-volatile memory element  
A three terminal non-volatile memory element includes a standard (low voltage) CMOS transistor, i.e. a storage transistor, having a drain coupled to a read bit line and a source connected to...
6242772 Multi-sided capacitor in an integrated circuit  
A dynamic random access memory. The memory includes a write transistor N3 and a read transistor N2. In a preferred embodiment the write transistor has a threshold level higher than the read...
6232634 Non-volatile memory cell and method for manufacturing same  
A non-volatile memory cell (81) includes a drain-side select transistor (86), a source-side select transistor (87), and a storage transistor (88). The drain-side select transistor (86) is adjacent...
6104639 Memory cell with stored charge on its gate and process for the manufacture thereof  
A memory cell with a stored charge on its gate, comprising (A) a channel forming region, (B) a first gate formed on an insulation layer formed on the surface of the channel forming region, the...
6034893 Non-volatile memory cell having dual avalanche injection elements  
A non-volatile memory cell includes a well region formed in a semiconductor substrate. First and second avalanche injection elements reside in the well region. A bifurcated floating-gate electrode...
6028789 Zero-power CMOS non-volatile memory cell having an avalanche injection element  
A zero-power non-volatile memory cell includes a control element, an avalanche injection element, and a CMOS inverter. A floating-gate electrode is capacitively coupled to the control element, the...
6016268 Three transistor multi-state dynamic memory cell for embedded CMOS logic applications  
Methods are disclosed in making a multi-state dynamic memory using a three transistor cell. The cell construction is consistent with a logic semiconductor process and is therefore useful for...
5909400 Three device BICMOS gain cell  
A nondestructive read, three device BICMOS gain cell for a DRAM memory having two FETs and one bipolar device. The gain cell has an improved access time (less latency), can operate for longer...
5841690 Semiconductor memory  
A semiconductor memory in which integration is enhanced is provided. An NMOS transistor Qn1 has a gate connected to a write word line WWLn, a source connected to a write bit line WBLn, and a drain...
5812476 Refresh circuit for DRAM with three-transistor type memory cells  
A semiconductor memory device of a three-transistor cell type dynamic random-access memory with improved performances includes a circuit arranged between a write bit line and a read bit line....
5808932 Memory system which enables storage and retrieval of more than two states in a memory cell  
A memory circuit which enables storage of more than two logic states in a memory cell. Since the additional logic states may be used to represent additional information bits, this memory circuit...
5761116 V.sub.pp only scalable EEPROM memory cell having transistors with thin tunnel gate oxide  
An enhanced, scalable EEPROM memory cell is provided with a structure having a plurality of half-height tunnel oxide depletion mode transistors. The structure further has individual wordlines...
5708598 System and method for reading multiple voltage level memories  
A system and method for reading multi-bit memory cells. The invention resides in employing a plurality of comparators to compare the voltage contained in a multi-bit memory cell with a reference...
5646903 Memory cell having a shared read/write line  
A DRAM memory having shared read/write lines. The DRAM memory is comprised of an array of 3T memory cells. Data is digitally stored in the form of capacitors that are either charged or discharged....
5532956 Memory cell structure for semiconductor device and dynamic semiconductor memory device  
A memory cell structure for a semiconductor device includes a capacitor for storing electric charge, a first transistor for controlling storage and release of charge in the capacitor, and a second...
5471087 Semi-monolithic memory with high-density cell configurations  
A memory is formed from an array of switchless integrated circuit memory cells in a high-density configuration. These cells comprise a capacitor and two diodes in a configuration where one diode is...
5438539 Memory device, method for reading information from the memory device, method for writing information into the memory device, and method for producing the memory device  
A memory device includes a first address signal line, a pair of second address signal lines, a standby signal line, and a memory cell provided at a cross point at which the first address signal...
5331590 Single poly EE cell with separate read/write paths and reduced product term coupling  
A single poly EE cell and an array using said cell, with the array being provided electrical connections such that the select gate for the read select transistor and the select gate for the write...
5296752 Current memory cell  
A current memory cell for sampling a current (I) at a current terminal (5) during a sample interval and for applying the current (I) to the current terminal (5) during a hold interval. A first...
4945393 Floating gate memory circuit and apparatus  
A floating gate memory device comprises a channel for conducting carriers from source to drain, a semiconductor heterostructure forming a potential well (floating gate) for confining carriers...
4935896 Semiconductor memory device having three-transistor type memory cells structure without additional gates  
A memory cell array (61) comprises a plurality of three-transistor type memory cells (10) arranged in a plurality of rows and columns. A plurality of pairs of write bit lines (WB1, WB2) and a...
4855955 Three transistor high endurance EEPROM cell  
The memory cell of the present invention is a three transistor cell, including two floating gate MOS transistors connected in series with a select transistor. The source of the first memory cell...
Matches 1 - 50 out of 81 1 2 >