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7142460 Flash memory device with improved pre-program function and method for controlling pre-program operation therein  
A flash memory device has an improved pre-program function. The flash memory device comprises memory cell blocks each including wordlines, bitlines, and memory cells sharing common source lines; an...
7139193 Non-volatile memory with two adjacent memory cells sharing same word line  
A nonvolatile semiconductor memory device having a small layout size includes a memory cell array in which a plurality of memory cells are arranged in a row direction and a column direction. The...
7139201 Non-volatile semiconductor memory device and memory system using the same  
The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are...
7136302 Integrated circuit memory device and method  
Structures and methods for DEAPROM memory with low tunnel barrier intergate insulators are provided. The DEAPROM memory includes a first source/drain region and a second source/drain region...
7136307 Write state machine architecture for flash memory internal instructions  
A system and method for a write state machine for non-volatile memory is disclosed. The write state machine has an associated read only memory for storing instructions for operation of the...
7133313 Operation scheme with charge balancing for charge trapping non-volatile memory  
A memory cell with a charge trapping structure has multiple bias arrangements. Multiple cycles of applying the bias arrangements lowering and raising a threshold voltage of the memory cell leave a...
7133316 Program/erase method for P-channel charge trapping memory device  
A method of operating a memory device is disclosed, wherein the memory device includes an n-type substrate and a plurality of memory cells formed thereon, each memory cell corresponding to a word...
7130240 Semiconductor memory system and method for multi-sector erase operation  
A semiconductor memory device is operable with a multi-sector erase mode for a multiplicity of memory chips, including a cell array, a register circuit containing information for a sector to be...
7130223 Nonvolatile semiconductor memory device  
Characteristics of a nonvolatile semiconductor memory device are improved. The memory cell comprises: an ONO film constituted by a silicon nitride film SIN for accumulating charge and by oxide...
7126856 Method and apparatus of memory clearing with monitoring RAM memory cells in a field programmable gated array  
A field-programmable gate array (FPGA) having an array of RAM memory cells comprising at least one row of RAM memory cells, each RAM cell of the at least one row of RAM memory cells coupled to a...
7127550 Multi-module simultaneous program, erase test, and performance method for flash memory  
Methods and apparatus for accessing modules on a flash memory package concurrently during testing are disclosed. According to one aspect of the present invention, a memory device for storing data...
7123518 Memory device  
A memory device including a plurality of word lines, a plurality of bit lines, at least four control lines and a plurality of memory cells is provided. The bit lines are disposed in a perpendicular...
7123517 Reprogrammable integrated circuit (IC) with overwritable nonvolatile storage  
A reprogrammable integrated circuit (IC) including overwritable nonvolatile storage cells. Cell contents are compared in a differential sense amplifier against a variable reference signal that has...
7116584 Multiple erase block tagging in a flash memory device  
A plurality of memory devices can be erase block tagged in parallel by issuing an erase pulse to memory devices that do not have memory blocks with erase block latches that indicate the block is...
7117295 Multilevel storage nonvolatile semiconductor memory device enabling high-speed data reading and high-speed data writing  
A nonvolatile semiconductor memory device transmits/receives data to/from a data input/output terminal every j bits (e.g., eight bits). Each of memory cells in a memory cell array can hold data of...
7113431 Quad bit using hot-hole erase for CBD control  
The present invention pertains to a technique for erasing bits in a dual bit memory in a manner that maintains complementary bit disturb control of bit-pairs of memory cells wherein each bit of the...
7113432 Compressed event counting technique and application to a flash memory system  
A non-volatile flash memory system counts the occurrences of an event, such as the number of times that individual blocks have been erased and rewritten, by updating a compressed count only once...
7113430 Device for reducing sub-threshold leakage current within a high voltage driver  
A device for reducing the effects of leakage current within electronic devices is disclosed. In one form, a high voltage driver includes a high voltage source coupled to at least one high voltage...
7113427 NVM PMOS-cell with one erased and two programmed states  
NVM cell for storing three levels of charge: one erased and two programmed states. The cell comprises a transistor structure providing a gate current versus gate voltage curve having a shape with a...
7110295 Semiconductor data processing device  
An erasing current is distributed to reduce a load of an internal power circuit and to decrease the number of drivers for erase. A semiconductor data processing device has: a memory array having...
7110301 Non-volatile semiconductor memory device and multi-block erase method thereof  
A non-volatile semiconductor memory device includes memory blocks and an erase controller configured to control a multi-block erase operation where at least two of the memory blocks are...
7106627 Nonvolatile semiconductor memory device with redundancy and security information circuitry  
A memory cell array has a first and a second storage area. The first storage area has memory elements selected by an address signal. The second storage area has memory elements selected by a...
7106629 Split-gate P-channel flash memory cell with programming by band-to-band hot electron method  
A split-gate, P-channel flash memory cell having a band-to-band hot electron (BBHE) programming method is defined to improve the endurance characteristics of performance of the cell. The...
7106625 Charge trapping non-volatile memory with two trapping locations per gate, and method for operating same  
A multiple-gate memory cell comprises a semiconductor body and a plurality of gates arranged in series on the semiconductor body. A charge storage structure on the semiconductor body includes two...
7103706 System and method for multi-bit flash reads using dual dynamic references  
A system and methodology is provided for proper reading of multi-bit memory cells in a memory device. A first reference cell and a second reference cell is employed to determine an average dynamic...
7102927 Memory devices and programming methods that simultaneously store erase status indications for memory blocks  
Methods are provided to program a memory device having a plurality of memory blocks. A first address for selecting a row of each of the memory blocks is generated according to a multi-page program...
7102931 Nonvolatile semiconductor memory apparatus and method of producing the same  
A nonvolatile semiconductor memory apparatus suitable to logic incorporation, by which a charge injection efficiency is high and hot electrons (HE) can be effectively injected at a low voltage is...
7099200 Nonvolatile semiconductor memory  
In a 3Tr. NAND including a cell unit constituted of one memory cell and two select gate transistors between which the cell is held, to renew data by a byte unit, at an erase time, a potential of a...
7098505 Memory device with multiple memory layers of local charge storage  
A multiple memory layer device has a plurality of stacked memory layers. Each of the memory layers has: a charge generating layer of p-type semiconductor material with a plurality of n-type...
7099192 Nonvolatile flash memory and method of operating the same  
A nonvolatile memory and a method of operating the same are proposed. The nonvolatile memory has single-gate memory cells, wherein a structure of a transistor and a capacitor is embedded in a...
7099220 Methods for erasing flash memory  
Methods for erasing flash memory using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a second polarity during an erase period.
7099198 Row decoder in flash memory and erase method of flash memory cell using the same  
A row decoder in a flash memory comprises a first switch to selectively couple a word line to a first voltage terminal, and a second switch to selectively couple the word line to a second voltage...
7099194 Error recovery for nonvolatile memory  
An error recovery technique is used on marginal nonvolatile memory cells. A marginal memory cell is unreadable because it has a voltage threshold (VT) of less than zero volts. By biasing adjacent...
7099199 Nonvolatile semiconductor memory device  
A nonvolatile memory apparatus which includes plural memories one of which is a nonvolatile memory such as a Flash EEPROM capable of being specified a plurality of operations from a processing unit...
7099195 Methods for neutralizing holes in tunnel oxides of floating-gate memory cells and devices  
Methods for neutralizing holes in tunnel oxides of floating-gate memory cells and devices using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a...
7099191 Channel erase type nonvolatile semiconductor memory device and electronic card and electronic apparatus using the device  
A channel erase flash memory including a redundancy word line group constituted of a plurality of redundancy word lines separately from a normal memory space of a memory cell array, and including a...
7095651 Non-volatile semiconductor memory device  
A memory cell has a selection transistor constituted of an MOS transistor having a gate electrode and a cell transistor constituted of an MOS transistor having the same polarity as the selection...
7095656 Method of erasing NAND flash memory device  
Provided is concerned with a method of erasing a NAND flash memory device, capable of restraining an erasing disturbance fail arising from a deselected cell block and improving a product yield of...
7092297 Method for pulse erase in dual bit memory devices  
The present invention provides a method for erasing floating gate memory devices. Specifically, one embodiment of the present invention discloses a method for erasing an array of non-volatile flash...
7092298 Methods of erasing a non-volatile memory device having discrete charge trap sites  
Methods of erasing a non-volatile memory device having discrete charge trap sites between a semiconductor substrate and a gate include applying a negative voltage to a gate at least partially...
7092296 Nonvolatile semiconductor memory  
Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the...
7088623 Non-volatile memory technology suitable for flash and byte operation application  
The present invention provides a non-volatile memory cell structure suitable for the flash memory cell and EEPROM cell (electrically erasable programmable read only memory cell) to perform the byte...
7088132 Configuring FPGAs and the like using one or more serial memory devices  
The configuration architecture for a programmable device, such as an FPGA, includes one or more memory devices connected directly to the FPGA such that the FPGA can be configured with configuration...
7085161 Non-volatile semiconductor memory with large erase blocks storing cycle counts  
In a flash EEPROM system that is divided into separately erasable blocks of memory cells with multiple pages of user data being stored in each block, a count of the number of erase cycles that each...
7082060 Soft programming for recovery of overerasure  
A method of erasing a memory cell includes the step of erasing a memory cell. The current in the memory cell is measured. If the measured memory cell current approximately exceeds a predetermined...
7079448 Word-programmable flash memory  
The present invention relates to a memory in integrated circuit comprising a central Flash-type memory comprising memory cells forming pages, a buffer memory capable of storing binary words, and a...
7079437 Nonvolatile semiconductor memory device having configuration of NAND strings with dummy memory cells adjacent to select transistors  
A nonvolatile semiconductor memory device having a plurality of electrically rewritable nonvolatile memory cells connected in series together is disclosed. A select gate transistor is connected in...
7079424 Methods and systems for reducing erase times in flash memory devices  
A method is provided for erasing a memory cell having a substrate, a control gate, a floating gate, a source region and a drain region. The method includes pre-programming the memory cell to raise...
7079423 Method for programming dual bit memory devices to reduce complementary bit disturbance  
The present invention provides a method for programming a selected bit in a memory cell of a non-volatile dual bit flash memory device. The method includes applying a positive voltage to a bit line...
7080192 File storage and erasure in flash memory  
A non-volatile, multi-bit-per-cell, Flash memory uses a storage process and/or architecture that is not sector-based. A data block can be stored without unused storage cells remaining in the last...
Matches 301 - 350 out of 1338 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >