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7236405 Method for setting erasing pulses and screening erasing defects of nonvolatile memory  
Method for determining the number of applications of erasing pulses, including extracting two pairs of the accumulated number of the erasing pulses Np and the ratio Re of the number of erased...
7236398 Structure of a split-gate memory cell  
A split-gate memory cell includes a memory transistor and a select transistor. The memory transistor includes a drain, a source, a control gate and a floating gate. The select transistor includes a...
7233525 Method of converting contents of flash memory cells in the presence of leakage  
An erase operation in a flash memory device includes applying an erase pulse to memory cells of the flash memory device to convert the contents of the memory cells into logic 1 bits before any...
7233529 System for erasing nonvolatile memory  
Erasing is performed with respect to a nonvolatile memory cell without causing depletion halfway therethrough. A control circuit for reversibly and variably controlling the threshold voltage of the...
7230853 Selective erase method for flash memory  
Selective erase method for a flash memory device including a group of memory cells arranged in rows and columns include performing an erase operation on the group of memory cells and verifying the...
7230851 Reducing floating gate to floating gate coupling effect  
For a non-volatile memory system, compressing the erase threshold voltage distribution into the lowest threshold voltage state will decrease the valid data threshold voltage window. Decreasing the...
7227787 Method for erasing an NROM cell  
An operation to erase a nitride read only memory (NROM) memory block starts by erasing the memory block. An erase verify operation can then be performed to determine the success of the erase. If a...
7227784 Nonvolatile semiconductor memory device performing erase operation that creates narrow threshold distribution  
A nonvolatile semiconductor memory device includes a control circuit configured to perform a first block erase operation that erases nonvolatile memory cells together in a lump such that threshold...
7224618 Nonvolatile semiconductor memory device with erase voltage measurement  
A nonvolatile semiconductor memory device is provided comprising a plurality of memory cell arrays, each of which consists mainly of sidewall type memory cells arranged in a matrix, the memory cell...
7224620 CAcT-Tg (CATT) low voltage NVM cells  
Described herein are the methods the CACT and TG Non-volatile program erase methods, for programming and erasing NVM cells. This combination allows use of low voltage methods for program, and...
7221597 Ballistic direct injection flash memory cell on strained silicon structures  
A flash memory cell comprising a silicon-germanium layer with a pair of source/drain regions. A strained silicon layer is formed over the silicon-germanium layer such that the pair of source/drain...
7221593 Non-volatile memory device with erase address register  
A non-volatile memory device includes an array of non-volatile memory cells. The memory has control circuitry to erase the non-volatile memory cells and perform erase verification operations. The...
7218555 Imaging cell that has a long integration period and method of operating the imaging cell  
The integration period of an imaging cell, or the time that an imaging cell is exposed to light energy, is substantially increased by utilizing a single-poly, electrically-programmable,...
7215576 Nonvolatile semiconductor memory device which erases data in units of one block including a number of memory cells, and data erasing method of the nonvolatile semiconductor memory device  
In a data erasing method of a nonvolatile semiconductor memory device, cells are subjected to the processings of executing programming by applying a voltage to the cells to set their threshold...
7209390 Operation scheme for spectrum shift in charge trapping non-volatile memory  
A memory cell with a charge trapping structure is programmed using refill cycles that include a program pulse followed by a charge balancing pulse that causes ejection of electrons from the charge...
7209386 Charge trapping non-volatile memory and method for gate-by-gate erase for same  
A multiple-gate memory cell comprises a semiconductor body and a plurality of gates arranged in series on the semiconductor body. A charge storage structure on the semiconductor body includes...
7209252 Memory module, printer assembly, and method for storing printer code  
A memory module, a printer assembly, and a method for storing a computer code for a printer-controller application specific integrated circuit (ASIC) having a non-ROM memory control. The memory...
7206230 Use of data latches in cache operations of non-volatile memories  
Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the inter-phase pipelining of operations with the same memory, allowing, for example, a read...
7200040 Method of operating p-channel memory  
A method of operating a P-channel memory is described. The P-channel memory includes a substrate, a gate formed over the substrate, a charge trapping structure disposed between the substrate and...
7200047 High voltage positive and negative two-phase discharge system and method for channel erase in flash memory devices  
An erase discharge circuit in a flash memory is coupled to an array source and a p-well drive and receives first and second discharge signals. The erase discharge circuit operates during a...
7200049 Methods for accelerated erase operations in non-volatile memory devices and related devices  
Memory cells in a memory cell array are erased using an erase operation followed by a post-program operation. In the erase operation, an erase voltage is applied to a plurality of memory cells of...
7196929 Method for operating a memory device having an amorphous silicon carbide gate insulator  
A floating gate transistor has a reduced barrier energy at an interface with an adjacent amorphous silicon carbide (a-SiC) gate insulator, allowing faster charge transfer across the gate insulator...
7196934 Non-volatile memory with erase verify circuit having comparators indicating under-erasure, erasure, and over-erasure of memory cells  
A memory device verify system determines a state of memory cells in a memory. The memory includes a memory array having a plurality of memory cells coupled to bit lines. A verify circuit is coupled...
7193902 Method of erasing a flash memory cell  
Methods are disclosed for erasing a flash memory cell including: (a) a semiconductor substrate, (b) a gate, (c) a source, (d) a drain, (e) a well, the gate including: (1) a tunnel oxide film, (2) a...
7190621 Sensing scheme for a non-volatile semiconductor memory cell  
A method of sensing a state of a non-volatile semiconductor memory cell is provided. A memory cell current as well as a comparative current generated from at least one reference cell are compared...
7187591 Memory device and method for erasing memory  
A memory array includes a coupled controller for controlling the writing to, reading from and erasure of memory cells and blocks of memory cells within the memory array. The controller is operable...
7184313 Method circuit and system for compensating for temperature induced margin loss in non-volatile memory cells  
The present invention consists of a method and system for compensating, over time and over an operating temperature range, for margin loss in a non-volatile memory (“NVM”) cell, which method...
7184319 Method for erasing non-volatile memory cells and corresponding memory device  
The invention relates to a method for erasing non-volatile memory cells, and to a corresponding non-volatile memory device of the programmable and electrically erasable type implementing the...
7184316 Non-volatile memory cell array having common drain lines and method of operating the same  
A nonvolatile memory cell array having common drain lines and method of operating the same are disclosed. A positive voltage is applied to a gate of a selected cell and gates of memory cells that...
7180777 System and method for destructive purge of memory device  
A memory purge system destructively purges the memory circuits of a memory device. The system includes a power supply for supplying a selectable voltage and current. Switching circuits electrically...
7177975 Card system with erase tagging hierarchy and group based write protection  
A low cost data storage and communication system is disclosed. The low cost data storage and communication system has a host and at least one card connected to the host. A voltage negotiator...
7177200 Two-phase programming of a flash memory  
A datum is stored in a memory by placing a memory cell in a first state that is indicative of the datum, and later placing the same or a different cell in a second state that is indicative of the...
7177198 Compensated method to implement a high voltage discharge phase after erase pulse in a flash memory device  
A method for discharge in a flash memory device includes: initiating a discharge of a memory cell after an erase operation; coupling a first discharge circuit to a first plate of a gate-bulk...
7177190 Combination nonvolatile integrated memory system using a universal technology most suitable for high-density, high-flexibility and high-security sim-card, smart-card and e-passport applications  
A combination EEPROM, NOR-type Flash and NAND-type Flash nonvolatile memory contains memory cells in which a floating gate transistor forms a NAND-type Flash nonvolatile memory cell, forms a...
7173852 Corrected data storage and handling methods  
In order to maintain the integrity of data stored in a flash memory that are susceptible to being disturbed by operations in adjacent regions of the memory, disturb events cause the data to be...
7173861 Nonvolatile memory device for preventing bitline high voltage from discharge  
According to some embodiments, a nonvolatile semiconductor memory device includes high voltage circuits that prevent high voltages, which are applied to bitlines during an erase operation, from...
7170795 Electrically erasable charge trap nonvolatile memory cells having erase threshold voltage that is higher than an initial threshold voltage  
An electrically erasable charge trap nonvolatile memory cell has an initial threshold voltage, a program voltage that is higher than the initial threshold voltage, and an erase threshold voltage...
7170796 Methods and systems for reducing the threshold voltage distribution following a memory cell erase  
A method is provided for erasing a memory device including a number of memory cells, the memory cells including a substrate, a control gate, a charge storage element, a source region and a drain...
7167399 Flash memory device with a variable erase pulse  
A method of operating a flash memory device according to an embodiment of the present invention includes selecting a flash cell in a flash memory device to undergo an erase, applying a long erase...
7167398 System and method for erasing a memory cell  
A method erases a memory cell of a semiconductor device that includes a group of memory cells. Each memory cell includes a group of storage regions. The method includes determining that each...
7164610 Microcomputer having a flush memory that can be temporarily interrupted during an erase process  
A microcomputer with a built-in non-volatile semiconductor memory, which can automatically perform a work of temporarily interrupting automatic writing or automatic erase and accepting an...
7161835 Non-volatile semiconductor memory device  
A semiconductor memory device including: a cell array with electrically rewritable and non-volatile memory cells arranged therein; a sense amplifier circuit configured to read data of and write...
7161842 Flash memory device and method of erasing flash memory cell thereof  
A flash memory device and method of erasing flash memory cells thereof are provided. The erase of a cell block unit or a page unit is effected by a word line switch included in a predecoder...
7161840 Erase method in flash memory device  
An erase method in a flash memory device by which over-erase of the flash memory device is prevented. The method includes applying an electric field to a structure between the control gate and the...
7161841 Method for erasing programmable interconnect cells for field programmable gate arrays using reverse bias voltage  
A method for erasing a non-volatile memory cell interconnect switch in an FPGA comprises providing an FPGA having a core containing a plurality of non-volatile-memory-cell interconnect switches,...
7158411 Integrated code and data flash memory  
A memory architecture for an integrated circuit comprises a first memory array configured to store data for one pattern of data usage and a second memory array configured to store data for another...
7158416 Method for operating a flash memory device  
An error correction code is applied and an erasing procedure is passed as accomplished, if a maximum number of single bit failures in compliance with a criterion of the error correction code is not...
7155357 Method and apparatus for detecting an unused state in a semiconductor circuit  
An unused state detection circuit is disclosed that detects an unused state in a semiconductor circuit. A semiconductor circuit is “unused” when the unused state detection circuit has not been...
7151697 Non-volatile semiconductor memory  
A non-volatile semiconductor memory includes a substrate having a substrate region, at least one word line, a plurality of non-volatile memory cells arranged in a plurality of sectors and further...
7149126 Process for making and programming and operating a dual-bit multi-level ballistic MONOS memory  
A fast low voltage ballistic program, ultra-short channel, ultra-high density, dual-bit multi-level flash memory is described. The structure and operation of this invention is enabled by a twin...
Matches 251 - 300 out of 1341 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >