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7460396 Semiconductor device  
In a data program/erase device of a nonvolatile memory cell, data are re-written by means of an FN tunnel current of an entire channel surface. In a buried n-well of a semiconductor substrate in a...
7460411 Array source line (AVSS) controlled high voltage regulation for programming flash or EE array  
A method for programming a Flash memory array comprises coupling at least one of a current source and a potential source to at least one selected bitline of a Flash memory array, monitoring a...
7460410 Nonvolatile semiconductor memory device and programming or erasing method therefor  
In a nonvolatile memory cell having a trap layer, programming or erasing is made in a sequence of first charge injection with a given wait time being secured and second charge injection executed...
7457168 Non-volatile memory device and associated method of erasure  
Disclosed is a non-volatile memory device and a method of erasing the non-volatile memory device. An erase voltage is simultaneously applied to a plurality of sectors contained in the non-volatile...
7457156 NAND flash depletion cell structure  
NAND architecture Flash memory strings, memory arrays, and memory devices are described that utilize depletion mode floating gate memory cells. Depletion mode floating gate memory cells allow for...
7457166 Erase voltage manipulation in non-volatile memory for controlled shifts in threshold voltage  
The erase voltage applied to a set of non-volatile storage elements being erased is structured to provide controlled shifts in the threshold voltage of the storage elements. The erase voltage is...
7454558 Non-volatile memory with erase block state indication in data section  
An improved Flash memory device with a distributed erase block management (EBM) scheme is detailed that enhances operation and helps minimize write fatigue of the floating gate memory cells of the...
7453736 Methods of erasing and designing electrically erasable charge trap nonvolatile memory cells having erase threshold voltage that is higher than an initial threshold voltage  
An electrically erasable charge trap nonvolatile memory cell has an initial threshold voltage, a program voltage that is higher than the initial threshold voltage, and an erase threshold voltage...
7453731 Method for non-volatile memory with linear estimation of initial programming voltage  
In a non-volatile memory, a selected page on a word line is successively programmed by a series of voltage pulses of a staircase waveform with verifications in between the pulses until the page is...
7450433 Word line compensation in non-volatile memory erase operations  
Compensation voltage(s) are applied to a non-volatile memory system during erase operations to equalize the erase behavior of memory cells. Compensation voltages can compensate for voltages...
7450436 Device recoverable purge for flash storage device  
A flash storage device includes flash storage units that are purged in response to a condition or command while allowing the flash storage device to be used subsequent to the purge. A flash...
7450434 Semiconductor device and its control method  
A semiconductor device includes sectors having memory cells connected to local word lines, decoders selecting the sectors, and a circuit generating, in erasing of a selected sector, a control...
7450418 Non-volatile memory and operating method thereof  
An operating method of a non-volatile memory is provided. The non-volatile memory includes plural memory cells. Each memory cell includes a charge storage structure, a gate, and a source and a...
7447072 Storage device employing a flash memory  
A semiconductor disk wherein a flash memory into which data is rewritten in block unit is employed as a storage medium, the semiconductor disk including a data memory in which file data are stored,...
7447073 Method for handling a defective top gate of a source-side injection flash memory array  
A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high...
7447087 Semiconductor memory device having memory block configuration  
A memory array including memory mats is arranged in a U shape when seen in two dimensions, and a logic circuit and an analog circuit are arranged in a region unoccupied by the memory array. This...
7447080 Method and device for checking the execution of a write command for writing in a memory  
A method for executing a write command for writing a binary word in a programmable memory, comprises writing each of the bits in a programmed state of a binary word to be written in a corresponding...
7443731 Semiconductor nonvolatile memory device  
An operation scheme for operating stably a semiconductor nonvolatile memory device is provided. When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate...
7440311 Single-poly non-volatile memory cell  
A non-volatile memory cell includes a floating gate transistor having a floating gate coupled to a metal layer capacitor defined in one or more metal layers. Within each metal layer, the metal...
7436707 Flash memory cell structure and operating method thereof  
A flash memory cell structure has a substrate, a select gate, a first-type doped region, a shallow second-type doped region, a deep second-type doped region, and a doped source region. The...
7433244 Flash memory device and related erase operation  
An erase operation for a flash memory device includes identifying a sector group including a plurality of sectors based on an address, simultaneously pre-programming the sectors in the sector...
7433233 NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same  
An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of...
7430138 Erasing non-volatile memory utilizing changing word line conditions to compensate for slower erasing memory cells  
Voltage conditions applied to the memory cells of a non-volatile memory system are changed during erase operations in order to equalize the erase behavior of the select memory cells with other...
7428174 Semiconductor flash memory  
A semiconductor flash memory includes an erase/write control unit that, when performing an erase/write operation of read memory cells, reads and senses memory current of the read memory cells for...
7423912 SONOS memory array with improved read disturb characteristic  
A PMOS non-volatile memory array using SONOS transistors having program and erase threshold voltages for representing digital logic states of zero and one and selected to optimize read disturb...
7423922 Defective block handling in a flash memory device  
A method and circuit that remaps, to a single redundant memory block, defective rows from amongst a plurality of defective memory blocks. The circuit determines which rows of each memory block is...
7423913 Structures and methods for enhancing erase uniformity in a nitride read-only memory array  
A virtual ground nitride read-only memory array has a matrix of nitride read-only memory cells in which during an erase operation the non-erasing side of nitride read-only memory cells are...
7423903 Single-gate non-volatile memory and operation method thereof  
A single-gate non-volatile memory and an operation method thereof, wherein a transistor and a capacitor structure are embedded in a semiconductor substrate; the transistor comprises: a first...
7420853 Semiconductor storage device and semiconductor storage device driving method  
A semiconductor storage device comprises a semiconductor layer; a plurality of memory cells formed on the semiconductor layer, data writing, erasing or reading with respect to each of the memory...
7420848 Method, system, and circuit for operating a non-volatile memory array  
A method and a system for operating bits of memory cells in a memory array, the method including applying a first operating pulse to a terminal of a first cell, the first operating pulse is...
7414909 Nonvolatile semiconductor memory  
There is provided a high-density mask ROM operable at a high speed. With the mask ROM, respective source lines are disposed so as to be shared by memory cells in respective columns adjacent to each...
7414893 EEPROM memory architecture  
An electrically erasable and programmable memory in which control gate transistors have been suppressed includes memory cells each with an access transistor and a floating gate transistor. A word...
7414889 Structure and method of sub-gate and architectures employing bandgap engineered SONOS devices  
A bandgap engineered SONOS device structure for design with various AND architectures to perform a source side injection programming method. The BE-SONOS device structure comprises a spacer oxide...
7411833 Nitride trapping memory device and method for reading the same  
A nitride trapping memory device includes a comparator, a bias unit, a memory cell, a cycling cell, a compensation cell and a control unit. The comparator has a reference voltage. The bias unit is...
7411824 Semiconductor memory device capable of increasing writing speed  
A memory cell array has a structure in which a plurality of memory cells connected with word lines and bit lines and connected in series are arranged in a matrix form. A selection transistor...
7408813 Block erase for volatile memory  
A system and method for erasing a block of data in a plurality of memory cells includes clamping one of a digit line and an I/O line in a sensing circuit of a memory device to a fixed logic level....
7405979 Nonvolatile memory system, semiconductor memory, and writing method  
A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing...
7405976 Nonvolatile semiconductor memory and method for controlling the same  
A nonvolatile semiconductor memory includes a memory cell array, a flag information storage that stores a write flag indicating success/failure of writing in association with each address of a...
7403430 Erase operation for use in non-volatile memory  
A sector erase method for use in a non-volatile memory, such as a FLASH memory, including a plurality of memory cells in rows and columns, the memory cells being divided into a plurality of...
7403428 Systems for erasing non-volatile memory utilizing changing word line conditions to compensate for slower erasing memory cells  
Voltage conditions applied to the memory cells of a non-volatile memory system are changed during erase operations in order to equalize the erase behavior of the select memory cells with other...
7403427 Method and apparatus for reducing stress in word line driver transistors during erasure  
In a method of erasing flash memory cells, the flash memory cells organized in selectable memory blocks, the erasing step comprising applying an erase pulse voltage to a commonly biased cell well...
7403429 Method of erasing data with improving reliability in a nonvolatile semiconductor memory device  
A method of erasing data in a nonvolatile semiconductor memory device including applying an erase voltage to a substrate of the semiconductor memory device, applying a ground voltage to wordlines...
7403418 Word line voltage boosting circuit and a memory array incorporating same  
A first embodiment of a word line voltage boosting circuit for use with an array of non-volatile memory cells has a capacitor, having two ends, connected to the word line. One end of the capacitor...
7403424 Erasing non-volatile memory using individual verification and additional erasing of subsets of memory cells  
A set of non-volatile storage elements is divided into subsets for erasing in order to avoid over-erasing faster erasing storage elements. The entire set of elements is erased until a first subset...
7400538 NROM memory device with enhanced endurance  
The efficient removal of parasitic electron charges from the ONO structure of an NROM cell by periodically applying a negative gate refresh voltage in a way that injects holes from the substrate...
7400537 Systems for erasing non-volatile memory using individual verification and additional erasing of subsets of memory cells  
A set of non-volatile storage elements is divided into subsets for erasing in order to avoid over-erasing faster erasing storage elements. The entire set of elements is erased until a first subset...
7397703 Non-volatile memory with controlled program/erase  
A method for programming/erasing a non-volatile memory (NVM) includes performing a program/erase operation on a portion of the NVM using a first set of parameters. The method further includes...
7397699 Channel discharging after erasing flash memory devices  
A post-erase channel clearing procedure for double well, floating gate, non-volatile memory cells. The channel is cleared of charged particles coming from the floating gate after an erase operation...
7397706 Methods of erasing flash memory devices by applying wordline bias voltages having multiple levels and related flash memory devices  
Methods of erasing data in a flash memory device are provided in which a plurality of wordline bias voltages are generated that include wordline bias voltages having at least two different levels,...
7398554 Secure lock mechanism based on a lock word  
One or more lock words in a non-volatile memory with write ability correspond to lockable features of a protected system including the memory. A lockable feature should be locked when the...
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