|
Match
|
Document |
Document Title |
|
|
6442066 |
Flash memory with overerase protection
A non-volatile memory is described which includes an array of memory cells arranged in rows and columns. A split source line architecture is implemented and uses isolation transistors located...
|
|
|
6442073 |
Nonvolatile memory cell with multiple gate oxide thicknesses
A nonvolatile memory cell (500) has multiple oxide thicknesses, a tunnel oxide portion (625) and thicker gate oxide portion (630). The memory cell (500) may be used to form compact arrays of memory...
|
|
|
6442074 |
Tailored erase method using higher program VT and higher negative gate erase
A method and system for programming and erasing the normal bits of a memory array of dual bit memory cells is accomplished by programming at a substantially high delta VT and an erase pulse that...
|
|
|
6442075 |
Erasing method for nonvolatile semiconductor memory device capable of improving a threshold voltage distribution
In a first step, “application of an erasing pulse” and “verification” are conducted so that all the memory cells in an erasing-target block are set to 3V or less. Consequently, generation...
|
|
|
6434054 |
Non-volatile semiconductor memory device controlling the range of distribution of memory cell threshold voltages
A non-volatile semiconductor memory device according to the invention comprises a memory cell array having a plurality of non-volatile memory cells, and a write state machine controlling a voltage...
|
|
|
6429063 |
NROM cell with generally decoupled primary and secondary injection
A method of creating a nitride, programmable read only memory (NROM) cell includes the step of decoupling injection of channel hot electrons into a charge trapping layer of the NROM cell from...
|
|
|
6426897 |
Method of erasing a flash memory device
A method of erasing a flash memory device performs erase operation by hot carrier injection method, by applying a ground potential to a source and applying the bias from a high voltage to a low...
|
|
|
6424574 |
Method using multiple erasing processes to increase using times of a flash memory
The present invention provides a method of erasing data in a flash memory. The flash memory has a number of memory units for storing data. The method has involves repeatedly performing an erasing...
|
|
|
6421276 |
Method and apparatus for controlling erase operations of a non-volatile memory system
A non-volatile memory system having an array of 2-bit cells is provided, wherein each cell stores an odd bit and an even bit. An ERASE pulse is applied to either the odd bits or the even bits in...
|
|
|
6421273 |
Electrically erasable and programmable, non-volatile memory device
A memory device comprises at least one electrically erasable and programmable non-volatile memory cell, a bistable flip-flop, connected in parallel with the memory cell, and a switching device,...
|
|
|
6418061 |
Non-volatile semiconductor memory device permitting data-read operation performed during data-write/erase operation
A non-volatile semiconductor memory includes a plurality of memory areas, a control unit which performs a data-write or data-erase operation with respect to one of the memory areas, an...
|
|
|
6418062 |
Erasing methods by hot hole injection to carrier trap sites of a nonvolatile memory
A method of stably and uniformly erasing a non-volatile memory or memory array in a gate insulator in which carrier-trapping sites for carrier storage are furnished is described. A first method of...
|
|
|
6407947 |
Method of erasing a flash memory device
Methods of erasing a flash memory device are disclosed. After performing a first erasure operation, the methods perform a second erasure operation wherein an erasure pulse width or an erasure...
|
|
|
6407948 |
Circuit and method thereof for correcting over-erased flash memory cells
A flash memory circuit has a flash memory array and a processor. The flash memory array has a plurality of erasable flash memory cells. Each of the flash memory cells is electrically connected to a...
|
|
|
6400610 |
Memory device including isolated storage elements that utilize hole conduction and method therefor
A memory device is presented that utilizes isolated storage elements ( 200 ) in a floating gate structure, where tunneling holes ( 404 ) are used to program the device and tunneling electrons ( 504...
|
|
|
6400634 |
Technique for increasing endurance of integrated circuit memory
A method increases endurance of an array of memory cells which have an endurance specified according to the number of change cycles that the memory cell can endure within a performance tolerance....
|
|
|
6396742 |
Testing of multilevel semiconductor memory
In accordance with an embodiment of the present invention, a method for testing a multilevel memory includes: performing an erase operation to place a plurality of memory cells in an erased state;...
|
|
|
6388921 |
Nonvolatile semiconductor memory device with improved reliability and operation speed
A memory transistor for a lock bit, holding information on whether a memory block can be erased/reprogrammed, is provided in the same column as that of a plurality of dummy cells. Since a sub bit...
|
|
|
6385072 |
Content addressable memory using part of memory region to store data which should not be erased
A content addressable memory (CAM) includes a memory region containing a plurality of word memories, an address storage section for storing address data specifying a partial region of the memory...
|
|
|
6385093 |
I/O partitioning system and methodology to reduce band-to-band tunneling current during erase
A system is provided for reducing band-to-band tunneling current during Flash memory erase operations. The system includes a memory sector divided into (N) I/O subsectors, N being an integer, and a...
|
|
|
6385090 |
Semiconductor nonvolatile memory using floating gate
The present invention provides a semiconductor nonvolatile memory provided with a plurality of memory cells having floating gates, which enables an optimum erase operation, even when the erase rate...
|
|
|
6381179 |
Using a negative gate erase to increase the cycling endurance of a non-volatile memory cell with an oxide-nitride-oxide (ONO) structure
An erase operation is performed on a non-volatile memory cell with an oxide-nitride-oxide structure by using an initial negative gate erase voltage to improve the speed and performance of the...
|
|
|
6377491 |
Non-volatile memory for storing erase operation information
This invention is nonvolatile memory that has an ordinary memory cell region wherein ordinary data is stored and an erase information storage memory region wherein the information that shows the...
|
|
|
6377488 |
Fast-erase memory devices and method for reducing erasing time in a memory device
A non-volatile semiconductor memory device comprising a memory array, the memory array divided into a plurality of sectors, each sector comprising a plurality of memory cells, which can be...
|
|
|
6373750 |
Non-volatile memory which performs erasure in a short time
The present invention is a flash memory, wherein when erasing a plurality of sectors an erasure process of applying a normal erasure stress to one sector is performed, while at the same time, a...
|
|
|
6370065 |
Serial sequencing of automatic program disturb erase verify during a fast erase mode
A method for serial sequencing the automatic disturb erase verify (APDEV) function during a multiple sector fast erase mode. The fast erase mode allows a memory device to erase several sectors of...
|
|
|
6370064 |
Method of operating split gate-typed non-volatile memory cell and semiconductor memory device having the cells
Methods of operating non-volatile memory cells (e.g., EEPROM devices) include the use of negative substrate biases during programming and erasing operations. Theses methods include the step of...
|
|
|
6366501 |
Selective erasure of a non-volatile memory cell of a flash memory device
A method of selectively erasing an individual memory cell of an array of non-volatile memory cells by providing an array of non-volatile memory cells that includes a first non-volatile memory cell...
|
|
|
6363013 |
Auto-stopped page soft-programming method with voltage limited component
Method for soft-programming at least one floating gate memory cell in at least one page of a persistent memory device by converging the low threshold voltages of the several cells of the page...
|
|
|
6359810 |
Page mode erase in a flash memory array
In a sector in a flash memory array PAGE ERASE and MULTIPLE PAGE ERASE modes of operation are provided. In the PAGE ERASE and MULTIPLE PAGE ERASE modes of operation, a preferred tunneling potential...
|
|
|
6356482 |
Using negative gate erase voltage to simultaneously erase two bits from a non-volatile memory cell with an oxide-nitride-oxide (ONO) gate structure
An erase operation is performed on a non-volatile memory cell with an oxide-nitride-oxide structure having charge stored near both the source and drain. During the erase operation, a negative gate...
|
|
|
6356481 |
Row decoder for a nonvolatile memory with capability of selectively biasing word lines to positive or negative voltages
The row decoder includes, for each word line of the memory, a respective biasing circuit receiving at the input a row selection signal switching, in preset operating conditions, between a supply...
|
|
|
6353556 |
Method for operating non-volatile memory cells
A pre-erase/incremented erase mechanism is employed to reduce excessive tunnel oxide fields in flash memory cells. A variable conditioning signal removes charge from “fast” bits in the array,...
|
|
|
6353555 |
Flash memory device capable of minimizing a substrate voltage bouncing and a program method thereof
Disclosed is a nonvolatile semiconductor memory device which comprises a controller for controlling block select signal generators. The controller simultaneously activates the block select signal...
|
|
|
6351417 |
Non-volatile semiconductor memory device having a function for controlling the range of distribution of memory cell threshold voltages and method of erasing data thereof
A non-volatile semiconductor memory device according to the invention comprises a memory cell array having a plurality of non-volatile memory cells, and a write state machine controlling a voltage...
|
|
|
6349061 |
Non-volatile semiconductor memory
To assure collective erasure irrespectively of whether or not there is any faulty sector which is an object for redundancy. A non-volatile semiconductor memory having a plurality of regions of...
|
|
|
6347053 |
Nonviolatile memory device having improved threshold voltages in erasing and programming operations
A nonvolatile memory device having a predetermined threshold voltage is disclosed. In the nonvolatile memory device comprising a gate electrode including a control gate, a floating gate and a gate...
|
|
|
6345000 |
Flash memory permitting simultaneous read/write and erase operations in a single memory array
A non-volatile Flash memory simultaneously performs an erase operation and a write or read operation in the same array of memory cells. The memory has a row based sector architecture, i.e., sectors...
|
|
|
6344995 |
Circuit for controlling the potential difference between the substrate and the control gate on non-volatile memory and its control method
A circuit for controlling a non-volatile memory cell having a source, a drain, a control gate, and a bulk is disclosed. The control circuit comprises a voltage source, a first charge-pumping...
|
|
|
6335879 |
Method of erasing and programming a flash memory in a single-chip microcomputer having a processing unit and memory
A semiconductor device having and electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and...
|
|
|
6335882 |
Nonvolatile semiconductor memory device capable of erasing blocks despite variation in erasing characteristic of sectors
A power generating portion generates an erasing potential for an erasing operation with respect to information stored in a memory cell and variably generates a first potential applied to the...
|
|
|
6333871 |
Nonvolatile semiconductor memory including a controller for providing an improved reprogram operation
Externally supplied program data is latched into data latch circuits DLL and DLR. A judgment is made as to whether or not the latched program data corresponds to any threshold value of multi-levels...
|
|
|
6331951 |
Method and system for embedded chip erase verification
A method and system are disclosed for verifying memory cell erasure, which may be employed in association with a dual bit memory cell architecture. The method includes selectively verifying proper...
|
|
|
6331953 |
Intelligent ramped gate and ramped drain erasure for non-volatile memory cells
A method of erasing a memory cell that includes a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains a first...
|
|
|
6331952 |
Positive gate erasure for non-volatile memory cells
A method of erasing a memory cell that includes a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains a first...
|
|
|
6331954 |
Determination of misalignment for floating gates near a gate stack bending point in array of flash memory cells
For electrically determining the level of misalignment of floating gate structures closest to a gate stack bending point in an array of flash memory cells, a plurality of test flash memory cells...
|
|
|
6330633 |
Data processing method and apparatus
This invention relates to an information processing method and apparatus. A memory for storing information in block units, comprises a data region for storing data in block units and a first and a...
|
|
|
6324102 |
Radiation tolerant flash FPGA
A radiation tolerant flash memory cell switch includes a programming transistor switch coupled between two circuit nodes to be selectively connected to one another. A floating gate flash memory...
|
|
|
6317360 |
Flash memory and methods of writing and erasing the same as well as a method of forming the same
A flash memory is provided on a semiconductor substrate. A trench with corners is provided on a surface of the semiconductor substrate. A gate insulation film is provided on a surface within the...
|
|
|
6314043 |
Erasing and parallel rewriting circuit for memory cell blocks, particularly for analog flash cells, and related operating method
Circuit for erasing and rewriting blocks of memory cells and particularly of analog flash cells, including at least one row decoding circuit including at least two adder blocks, suitable to...
|