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6532165 Nonvolatile semiconductor memory and driving method thereof  
In NAND type nonvolatile semiconductor memory each memory cell is made of a dual gate transistor connected at one gate portion thereof to ferroelectrics, a plurality of such memory cells are...
6532171 Nonvolatile semiconductor memory capable of selectively erasing a plurality of elemental memory units  
A semiconductor memory such as a flash memory, which comprises at least one two-dimensional array of memory cells with a plurality of rows and columns of memory cells grouped in a plurality of...
6529417 Source regulation circuit for flash memory erasure  
A flash memory is described which uses floating gate transistors as memory cells. A source regulation circuit within the memory is described which generates a ramped reference voltage signal. The...
6529413 Method for preventing over-erasing of memory cells and flash memory device using the same  
Disclosed herein is an erase method of a flash memory device that comprises discrete first and second erase discrimination periods. An erase operation is carried out using a bulk stepping scheme...
6529415 Nonvolatile semiconductor memory device achieving shorter erasure time  
A nonvolatile semiconductor memory device includes a memory cell array, a control circuit which repeatedly perform an automatic erasure operation with respect to an entirety of the memory cell...
6529416 Parallel erase operations in memory systems  
An apparatus for and method of memory operation having a memory, a cache containing a plurality of entries with a plurality of the entries to be written to memory, a detector for detecting in the...
6525963 Programmable read-only memory and method for operating the read-only memory  
A programmable read-only memory and a method for operating the read-only memory are described. The memory contains at least one memory cell field with a plurality of memory cells, in addition to a...
6525970 Erase method for flash memory  
A method of erasing electrically a programmable memory cell which cell includes a transistor formed in a region of semiconductor material. The transistor has a source region, a drain region, a...
6515902 Method and apparatus for boosting bitlines for low VCC read  
A memory device is disclosed having a memory cell in electrical communication with a node, and operative to indicate a binary value associated with data stored in the memory cell during a read...
6515910 Bit-by-bit Vt-correction operation for nonvolatile semiconductor one-transistor cell, nor-type flash EEPROM  
A method to test the erase condition of memory cells in a memory array device is achieved. The method is further extended to methods to detect and correct under erase and over erase conditions. The...
6515905 Nonvolatile semiconductor memory device having testing capabilities  
Included are a memory cell array 10 , a sense amplifier 21 for determining a cell storage value by comparing a signal value read out from an addressed EEPROM cell with a reference value, a...
6512701 Erase method for dual bit virtual ground flash  
A system and methodology is provided for verifying erasure of one or more dual bit virtual ground memory cells in a memory device, such as a flash memory. Each of the dual bits have a first or...
6512699 Nonvolatile semiconductor memory device having a hierarchial bit line structure  
A nonvolatile semiconductor memory device comprising a plurality of memory cells each having a transistor including a floating gate electrode as a constituent are arranged on a silicon substrate in...
6510084 Column decoder with increased immunity to high voltage breakdown  
A column decoder in an electrically-erasable, programmable read-only memory applies a bias voltage to, or floats, the gates of selected transistors during an erasure operation. This reduces the...
6507522 Method for erasing memory cells in a nonvolatile memory  
A method for managing memory cells in a nonvolatile memory, such as a flash memory, includes detecting and intermediately programming fast-erased memory cells. All of the memory cells in a sector...
6507520 Nonvolatile memory system  
Externally supplied program data is latched into data latch circuits DLL and DLR. A judgment is made as to whether or not the latched program data corresponds to any threshold value of multi-levels...
6504765 Flash memory device and method of erasing the same  
The present invention relates to a flash memory device. The present invention relates to a flash memory device in which a capacitor of a given capacitance is connected between a bit line connected...
6504763 Nonvolatile semiconductor memory capable of random programming  
A nonvolatile semiconductor memory capable of random programming has a semiconductor substrate of a first conductivity type having a memory region, a deep ion well of a second conductivity type...
6501681 Using a low drain bias during erase verify to ensure complete removal of residual charge in the nitride in sonos non-volatile memories  
An erase-verify operation is performed on a nonvolatile memory cell with an oxide-nitride-oxide structure by using a low drain bias voltage to allow residual charge remaining in the nitride layer...
6498752 Three step write process used for a nonvolatile NOR type EEPROM memory  
The present invention discloses a novel method for erasing an ETOX type and an AND type NOR flash memory arrays. The operations of the methods includes block erase which increases the Vt of the...
6493264 Nonvolatile semiconductor memory, method of reading from and writing to the same and method of manufacturing the same  
A nonvolatile semiconductor memory including at least two cells each comprising: a floating gate formed on a semiconductor substrate with the intervention of a first insulating film; a split gate...
6493267 Nonvolatile semiconductor memory device having verify function  
A non-volatile semiconductor memory device comprises a flip-flop circuit for holding write data in one of first and second states, a bit line connected to the flip-flop circuit via a switching...
6493280 Method of reducing trapped holes induced by erase operations in the tunnel oxide of flash memory cells  
A method of erasing memory cells in a flash memory device that recombines holes trapped in the tunnel oxide (after an erase operation) with electrons passing through the tunnel oxide is disclosed....
6493262 Method for operating nonvolatile memory cells  
The present invention is directed at a new nonvolatile memory cell structure, and a new erase method and apparatus for operating this and other nonvolatile memory cells, with special emphasis on...
6490203 Sensing scheme of flash EEPROM  
There is provided a reading circuit and method for performing program verify, erase verify, and over-erase-correction verify modes of operations on a selected memory core cell in an array of Flash...
6490649 Memory device  
An addressable memory device for storing blocks of varying length, utilizes a write pointer ( 18 ) to indicate the address of the next location to which data are to be written and an erase pointer...
6490205 Method of erasing a non-volatile memory cell using a substrate bias  
A method of erasing a memory cell with a substrate that has a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains...
6483745 Non-volatile semiconductor memory device with defect detection  
A non-volatile semiconductor memory device for allowing a data writing operation to, a data reading operation from, and a data erasing operation from a plurality of non-volatile memory cells. The...
6483750 Flash EEPROM with on-chip erase source voltage generator  
A Flash EEPROM having negative voltage generator means for generating a negative voltage to be supplied to control gate electrodes of memory cells for erasing the memory cells. The Flash EEPROM...
6480420 Semiconductor memory device having source areas of memory cells supplied with a common voltage  
A semiconductor memory device having a plurality of memory cells, word lines and bit lines formed on a semiconductor substrate, where each of the memory cells includes a source area formed adjacent...
6480414 Multi-level memory cell  
A multi-level memory cell has a substrate, a first floating gate, a second floating gate and a control gate. A first doped region, a second doped region and a channel region located between the...
6477088 Usage of word voltage assistance in twin MONOS cell during program and erase  
In the prior arts a twin MONOS memory erase is achieved by applying a positive bias to the bit diffusion and a negative bias to the control gate. The other word gate and substrate terminals are...
6477632 Storage device and accessing method  
In order to access a memory cell array ( 1 ), an address translation table which stores a correspondence between logical and physical addresses, and an empty block table which specifies locations...
6473342 Methods of operating split-gate type non-volatile memory cells  
Methods of operating non-volatile memory cells (e.g., EEPROM devices) include the use of negative substrate biases during programming and erasing operations. Theses methods include the step of...
6469928 Nonvolatile semiconductor memory device with concurrent memory access and data locking  
A nonvolatile semiconductor memory device includes a plurality of memory cell array blocks including a first memory cell array block to which a data write operation is performed or from which a...
6466504 Compilable block clear mechanism on per I/O basis for high-speed memory  
A circuit for selectively erasing a semiconductor memory instance on a per I/O basis. The circuit is provided as a tilable architectural element in a memory compiler for the semiconductor memory...
6466484 Nonvolatile semiconductor memory device capable of suppressing reduction of bit line potential in write-back operation and erase method  
A nonvolatile semiconductor memory device selects a bit line while a word line is in a non-selected state, and self-selectively writes back only a cell in an overerased state on the selected bit...
6462990 Post erase repair to enhance performance in a flash memory  
A technique of performing post erase repair on a flash memory by identifying a leaky column after the flash memory is erased. The leaky column is repaired first by programming memory cells of the...
6459617 Method and circuitry for bank tracking in write command sequence  
A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The synchronous flash memory device...
6459640 Nonvolatile semiconductor memory and automatic erasing/writing method thereof  
A nonvolatile semiconductor memory includes a memory block composed of a memory array having a plurality of memory cells arranged in a matrix form, each of the memory cells being composed of a...
6459615 Non-volatile memory cell array with shared erase device  
A non-volatile memory device is disclosed which includes an erase device that is shared among an array of memory cells. Each of the memory cells in the array includes a control device coupled to a...
6456526 Non-volatile memory device operation in response to two different types of read commands and a write command which includes write verification  
A non-volatile memory device having a plurality of memory cells and a control circuit. The control circuit receives operation commands from outside the device and controls the operation of the...
6457093 Circuit and method to control operations of another circuit  
An integrated circuit includes trim circuitry to control operations of internal circuitry. The integrated circuit includes multiplex circuitry for coupling the trim circuitry to internal circuits...
6456537 Techniques for erasing an erasable programmable read only memory (EPROM) cell  
Techniques for improved erasing of an EPROM are described. As a method, a a drain potential of a first polarity is applied to the drain node of a selected memory cell having a first polarity...
6452839 Method for erasing data from a single electron resistor memory  
A memory device includes a plurality of cells, each having a first electrode coupled to a first location on semiconductor material, a second electrode coupled to a second location disposed away...
6452840 Feedback method to optimize electric field during channel erase of flash memory devices  
A method of erasing a flash memory device that improves reliability and reduces the decrease in erase speed. The state of erasure is determined either during an erase phase or a verify phase and...
6452836 Non-volatile memory device with erase cycle register  
A non-volatile memory device includes an array of non-volatile memory cells. The memory has control circuitry to apply erase voltage pulses to the non-volatile memory cells and perform erase...
6442066 Flash memory with overerase protection  
A non-volatile memory is described which includes an array of memory cells arranged in rows and columns. A split source line architecture is implemented and uses isolation transistors located...
6442073 Nonvolatile memory cell with multiple gate oxide thicknesses  
A nonvolatile memory cell (500) has multiple oxide thicknesses, a tunnel oxide portion (625) and thicker gate oxide portion (630). The memory cell (500) may be used to form compact arrays of memory...
6442074 Tailored erase method using higher program VT and higher negative gate erase  
A method and system for programming and erasing the normal bits of a memory array of dual bit memory cells is accomplished by programming at a substantially high delta VT and an erase pulse that...
Matches 651 - 700 out of 1338 < 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 >