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8184481 Memory devices and methods of their operation including selective compaction verify operations  
Memory devices and methods of their operation, where following an erasure of a string of memory cells, a selective compaction verify operation is performed on one or more, but less than all, of the...
8174885 High speed operation method for twin MONOS metal bit array  
The present invention provides a novel read method of twin MONOS metal bit or diffusion bit structure for high-speed application. In a first embodiment of the present invention, the alternative...
8174905 Programming orders for reducing distortion in arrays of multi-level analog memory cells  
A method for data storage includes predefining an order of programming a plurality of analog memory cells that are arranged in rows. The order specifies that for a given row having neighboring rows...
8169832 Methods of erase verification for a flash memory device  
Methods and apparatus are disclosed, such as those involving a flash memory device that includes a memory block. The memory block includes a plurality of data lines extending substantially parallel...
8171207 Adaptive hybrid density memory storage device and control method thereof  
The present invention discloses a control method of an adaptive hybrid density memory storage device suitable for locating a data to the storage device. The storage device includes a high density...
8169828 Semiconductor memory cell, method for manufacturing the same and method for operating the same  
A semiconductor memory cell, and method of manufacturing a semiconductor memory cell and an method of operating a semiconductor memory cell. A method of operating may include programming a...
8169835 Charge trapping memory cell having bandgap engineered tunneling structure with oxynitride isolation layer  
A band gap engineered, charge trapping memory cell includes a charge storage structure including a trapping layer. a blocking layer, and a dielectric tunneling structure including a thin tunneling...
8164656 Memory emulation in an image capture device  
An image capture device using a memory array that is directly addressed and non-volatile is disclosed. The memory array can be used to replace and emulate multiple memory types such as DRAM, SRAM,...
8161355 Automatic refresh for improving data retention and endurance characteristics of an embedded non-volatile memory in a standard CMOS logic process  
A method for selectively refreshing data in a nonvolatile memory array based on failure type detected by an error correction code. If the page is determined to be error-free, no refresh operation...
8149631 Non-volatile semiconductor storage device  
For data erase from an electrically erasable and programmable non-volatile memory cell, the following operations are performed: an erase operation to apply an erase pulse voltage to a memory cell...
8145830 Flash memory and method for a cache portion storing less bit per cell than a main portion  
A flash memory device includes a storage area having a main memory portion and a cache memory portion storing at least one bit per cell less than the main memory portion; and a controller that...
8144517 Multilayered nonvolatile memory with adaptive control  
A method and device for adaptive control of multilayered nonvolatile semiconductor memory are provided, the device including memory cells organized into groups and a control circuit having a...
8144522 Erasing flash memory using adaptive drain and/or gate bias  
A hot hole erase operation as described herein can be utilized for a flash memory device having an array of memory cells. The erase operation employs an adaptive erase bias voltage scheme where the...
8144515 Interleaved flash storage system and method  
A flash storage system accesses data interleaved among flash storage devices. The flash storage system receives a data block including data portions, stores the data portions in a data buffer, and...
8144511 Selective memory cell program and erase  
Techniques are disclosed herein for programming memory arrays to achieve high program/erase cycle endurance. In some aspects, only selected word lines (WL) are programmed with other WLs remaining...
8139417 Flash memory device and read method  
A flash memory device includes a word line decoder configured to receive a row address, and decode a selected word line and a neighboring non-selected word line corresponding to the row address...
8139414 Source side asymmetrical precharge programming scheme  
A method for programming NAND flash cells to minimize program stress while allowing for random page programming operations. The method includes asymmetrically precharging a NAND string from a...
8139421 Erase degradation reduction in non-volatile memory  
Methods for erasing a memory device and memory systems are provided, such as those including a non-volatile memory device is erased by using an intermediate erase step prior to a normal erase step....
8139410 Trap-charge non-volatile switch connector for programmable logic  
A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located...
8139416 Operation methods for memory cell and array for reducing punch through leakage  
A method for programming a first memory cell in a memory array. In a specific embodiment, each memory cell has a drain, a source, a channel, and a control gate overlying a charge storage material...
8134873 Flash memory device and programming/erasing method of the same  
A flash memory device includes a bulk region, first through nth memory cell transistors arranged in a row on the bulk region, first through nth word lines respectively connected to gates of the...
8134869 Semiconductor memory having electrically erasable and programmable semiconductor memory cells  
An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected...
8130555 Nonvolatile semiconductor storage device and method of erase verifying the same  
A nonvolatile semiconductor storage device including a NAND cell unit having a first and a second select gate transistor, a plurality of memory cell transistors series connected between the first...
8130554 Securely erasing flash-based memory  
A method is used in securely erasing flash-based memory. A new version of data is received for a logical location of a flash-based memory. An old version of the data of the logical location is...
8130550 Memory with sub-blocks  
A non-volatile memory comprising a NOR block with a first sub-block independently addressable from a second sub-block, the two sub-blocks sharing a physical substrate of the NOR block, and a first...
8130551 Extra dummy erase pulses after shallow erase-verify to avoid sensing deep erased threshold voltage  
An erase operation for non-volatile memory includes first and second phases. The first phase applies a series of voltage pulses to a substrate, where each erase pulse is followed by a verify...
8125830 Area-efficient electrically erasable programmable memory cell  
Electrically erasable programmable “read-only” memory (EEPROM) cells in an integrated circuit, and formed by a single polysilicon level. The EEPROM cell consists of a coupling capacitor and a com...
8125835 Memory architecture having two independently controlled voltage pumps  
In embodiments described herein, a memory architecture has an array of non-volatile memory cells and a pair of independently controlled voltage pumps. The pair of voltage pumps is coupled for...
8125836 Verifying an erase threshold in a memory device  
In one or more embodiments, a memory device is disclosed as having an erase verify operation that includes a negative bias on the p-well in which the memory cell or cells being erased are formed....
8120966 Method and apparatus for management of over-erasure in NAND-based NOR-type flash memory  
A method and apparatus for operating an array block of dual charge retaining transistor NOR flash memory cells by erasing the dual charge retaining transistor NOR flash memory cells to set their...
8116138 Memory device distributed controller system  
A memory device distributed controller circuit distributes memory control functions amongst a plurality of memory controllers. A master controller receives an interpreted command and activates the...
8116137 Memory cell operation  
Embodiments of the present disclosure provide methods, devices, modules, and systems for programming memory cells. One method includes determining a quantity of erase pulses used to place a group...
8116142 Method and circuit for erasing a non-volatile memory cell  
The present invention is a method, circuit and system for erasing a non-volatile memory cell. A shunting element (e.g. transistor) may be introduced and/or activated between bit-lines to which one...
8116143 Method of erasing memory cell  
An embodiment of a method of erasing a target memory cell includes grounding a selected word line commonly coupled to portions of a row of memory cells respectively formed on first well regions of...
8117375 Memory device program window adjustment  
In one or more embodiments, a memory device is disclosed as having an adjustable programming window having a plurality of programmable levels. The programming window is moved to compensate for...
8112573 Non-volatile memory with erase block state indication in a subset of sectors of erase block  
An improved Flash memory device with a distributed erase block management (EBM) scheme is detailed that enhances operation and helps minimize write fatigue of the floating gate memory cells of the...
8111573 Nonvolatile semiconductor memory device and method of controlling the same  
Provided is a nonvolatile semiconductor memory device capable of performing a writing action for a memory cell at high speed. The device includes a memory cell array having a first sub-bank and a...
8107299 Semiconductor memory and method and system for actuating semiconductor memory  
A semiconductor memory includes a memory cell having a cell transistor and a selection transistor, a control gate line coupled to a gate electrode of the cell transistor, a selection gate line...
8107297 Method of reading nonvolatile memory device and method of operating nonvolatile memory device  
A method of reading a nonvolatile memory device may include, after an nth erase operation is performed, reading dummy cells on which a program operation has been performed based on a first read...
8102719 Semiconductor memory device capable of compensating variation with time of program voltage  
A voltage generating circuit generates, at a time of write, a first voltage which is higher than a program voltage, and generates an erase voltage at a time of erase. A first transistor has a...
8098530 Systems and methods for erasing a memory  
Methods of erasing a memory, methods of operating a memory, memory devices, and systems. In one such method, an erase block is erased to an intermediate erase voltage before it is erased to a final...
8099545 Wear leveling in storage devices based on flash memories and related circuit, system, and method  
A wear leveling solution is proposed for use in a storage device based on a flash memory. The flash memory includes a plurality of physical blocks, which are adapted to be erased individually. A...
8098529 Memory device having buried boosting plate and methods of operating the same  
Memory devices are disclosed, such as those that include a semiconductor-on-insulator (SOI) NAND memory array having a boosting plate. The boosting plate may be disposed in an insulator layer of...
8094495 Nonvolatile memory device  
A nonvolatile memory device includes a data memory cell array having multi level memory cells divided into two groups, a write sequence memory cell array configured to store a write sequence...
8094498 Nonvolatile semiconductor memory device  
In a nonvolatile semiconductor memory device storing data by accumulating charges in a floating gate, memory units, each of which includes a first MOS transistor as a read device, a bit cell...
8094501 Semiconductor memory device which includes memory cell having charge accumulation layer and control gate  
A semiconductor memory device includes memory cells, a source line, a word line, a bit line, and a driver circuit. The memory cells are formed on a semiconductor layer and have a charge...
8089809 Trap-charge non-volatile switch connector for programmable logic  
A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located...
8089808 Nonvolatile semiconductor memory device, and reading method, writing method and erasing method of nonvolatile semiconductor memory device  
A nonvolatile semiconductor memory including a memory cell array of memory cells arranged in a matrix, each of which includes a selective transistor and a memory cell transistor; the first column...
8081514 Partial speed and full speed programming for non-volatile memory using floating bit lines  
Partial speed and full speed programming are achieved for a non-volatile memory system. During a program operation, in a first time period, bit lines of storage elements to be inhibited are...
8081513 NAND flash memory  
A NAND flash memory has a control circuit. The control circuit applies a writing voltage between a control gate and a well by applying a first voltage to the well and a positive second voltage...
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