Match Document Document Title
9036428 Partial block erase for a three dimensional (3D) memory  
A method includes, at a non-volatile memory having a three dimensional (3D) memory configuration, performing an erase operation. Performing the erase operation includes providing a first control...
9019769 Semiconductor device and manufacturing method and operating method for the same  
A semiconductor device and a manufacturing method and an operating method for the same are provided. The semiconductor device comprises a substrate, a doped region and a stack structure. The doped...
9007837 Non-volatile memory system with reset control mechanism and method of operation thereof  
A method of operation of a non-volatile memory system includes: providing a control field effect transistor having a source electrode and a body-tie electrode; coupling a resistive storage element...
9007831 Memory devices with different sized blocks of memory cells and methods  
In an embodiment, each block of a plurality of blocks includes a respective plurality of strings of memory cells, where each of the plurality of strings of a block is coupled to a respective...
9001586 Semiconductor memory device capable of preventing degradation of memory cells and method for erasing the same  
A semiconductor memory device according to an embodiment of the present invention may include a memory cell array having a plurality of memory cells, a pass transistor group having normal pass...
8995190 Reducing the programming current for memory matrices  
A sector of an electrically programmable non-volatile memory includes memory cells connected to word lines and to bit lines, each cell including at least one transistor having a gate connected to...
8988947 Back bias during program verify of non-volatile storage  
Different back bias (or body bias) conditions are applied to a non-volatile storage system during different program verify operations of a programming operation. A back bias may be applied during...
8982633 Techniques for providing a direct injection semiconductor memory device  
Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor...
8971127 NAND flash memory programming  
A method of charging a floating gate in a nonvolatile memory cell comprises bringing a substrate channel within the memory cell to a first voltage, bringing a control gate to a programming...
8964475 Memory cell string based on gated-diode cell and memory array using the same  
The present invention provides a nonvolatile memory cell string and a memory array using the same. According to the present invention, a wall type semiconductor separated into twin fins and a...
8964480 Detecting programmed word lines based on NAND string current  
A number (Nwl) of programmed word lines in a block of NAND strings is determined by measuring a reference combined current (Iref) in the block when all of the memory cells are in a conductive...
8953371 Semiconductor storage device  
A semiconductor storage device has a plurality of memory cells each having a control gate that are formed on a well. The semiconductor storage device has a control circuit that applies a voltage...
8953382 Vertical nonvolatile memory devices and methods of operating same  
Integrated circuit memory devices include a plurality of vertically-stacked strings of nonvolatile memory cells having respective vertically-arranged channel regions therein electrically coupled...
8947965 Techniques for providing a direct injection semiconductor memory device  
Techniques for providing a direct injection semiconductor memory device are disclosed. In one exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device...
8942034 System and method of programming a memory cell  
A method includes selectively creating a first breakdown condition and a second breakdown condition at a semiconductor transistor structure. The first breakdown condition is between a source...
8934296 Dual-port semiconductor memory and first in first out (FIFO) memory having electrically floating body transistor  
Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor...
8928062 Nonvolatile semiconductor memory device and manufacturing method thereof  
A nonvolatile semiconductor memory device includes a plurality of nonvolatile memory cells formed on a semiconductor substrate, each memory cell including source and drain regions separately...
RE45307 Non-volatile semiconductor storage device  
A non-volatile semiconductor storage device includes: a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and a plurality of transfer...
8923064 Semiconductor memory device and method of operating the same  
A semiconductor memory device includes a memory array including a plurality of memory cells, and a peripheral circuit configured to perform an erase operation by supplying a first erase voltage to...
8917554 Back-biasing word line switch transistors  
Word line switch transistors in a well in a substrate may be back biased. A memory array having non-volatile storage devices may be in a separate well in the substrate. The well of the word line...
8917555 Semiconductor device and operating method thereof  
There is disclosed an operating method of a semiconductor device including programming a memory cell by supplying a program voltage to a control gate of the memory cell and a detrap voltage to a...
8873294 Nonvolatile memory devices, erasing methods thereof and memory systems including the same  
Provided are erase methods for a memory device which includes a substrate and multiple cell strings provided on the substrate, each cell string including multiple cell transistors stacked in a...
8861273 Bandgap engineered charge trapping memory in two-transistor nor architecture  
A 2T cell NOR architecture based on the use of BE-SONOS for embedded memory includes memory cells having respective access transistors having access gates and memory transistors having memory...
8848452 Erase verification circuitry for simultaneously and consecutively verifying a plurality of odd and even-numbered flash memory transistors and method thereof  
Embodiments described herein generally relate to verifying that a FLASH memory has been erased. In an embodiment, a method of erase verifying a memory column of a FLASH memory includes applying a...
8848456 Nonvolatile memory device, erasing method thereof, and memory system including the same  
Provided is an erasing method of a nonvolatile memory device. The erasing method applies a word line erase voltage to a plurality of word lines connected to the memory cells respectively, applies...
8839073 Zero-one balance management in a solid-state disk controller  
An SSD controller maintains a zero count and a one count, and/or in some embodiments a zero/one disparity count, for each read unit read from an SLC NVM (or the lower pages of an MLC). In an event...
8837227 Non-volatile semiconductor device, and method of operating the same  
A non-volatile semiconductor device and a method for operating the same are disclosed, where the non-volatile semiconductor device includes a gate dielectric layer, a p-type floating gate, a...
8824210 Hot electron injection nanocrystals MOS transistor  
The disclosure relates to a hot electron injection MOS transistor, comprising source and drain regions formed in a semiconductor substrate, a control gate, and a floating gate comprising...
8817538 Nonvolatile semiconductor memory device and method for erasing data thereof  
A control circuit is configured to set a drain-side select transistor and a source-side select transistor connected to a selected memory string to non-conductive states. The control circuit is...
8787082 Semiconductor memory device comprising three-dimensional memory cell array  
A semiconductor memory device includes a substantially planar substrate; a memory string vertical to the substrate, the memory string comprising a plurality of storage cells; and a plurality of...
RE45036 Semiconductor memory device  
A semiconductor memory device includes a first first-type well including a first cell array for storing a data to apply the data to one of a first bit line and a first bit line bar, and a first...
8767458 Dual-port semiconductor memory and first in first out (FIFO) memory having electrically floating body transistor  
Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor...
8760928 NAND flash biasing operation  
A charge storage memory is configured in a NAND array, and includes NAND strings coupled to bit lines via string select switches and includes word lines. A controller is configured to produce a...
8760917 Non-volatile memory cell with high bit density  
A non-volatile memory cell with high bit density is disclosed. Embodiments include: providing a transistor having a wordline gate structure over a substrate, first and second floating gate...
8760927 Efficient static random-access memory layout  
A complementary metal-oxide-semiconductor (CMOS) static random access memory (SRAM) with no well contacts within the memory array. Modern sub-micron CMOS structures have been observed to have...
8743611 Non-volatile semiconductor memory device  
A first capacitor includes a plurality of first conductive layers and second conductive layers. The first conductive layers function as a first electrode of the first capacitor, the second...
8724398 Non-volatile semiconductor device, and method of operating the same  
A non-volatile semiconductor device and a method for operating the same are disclosed, where the non-volatile semiconductor device includes a gate dielectric layer, a n-type floating gate, a...
8705290 Memory device having improved programming operation  
Some embodiments include methods and devices having a module and memory cells. The module is configured to reduce the amount of electrons in the sources and drains of the memory cells during a...
8699270 System and method for controlling voltage ramping for an output operation in a semiconductor memory device  
A voltage driving circuit comprises a current bias generating unit and a voltage driving unit. The current bias generating unit is configured to receive a mode signal and to generate a mode...
8699274 Flash memory device and operating method for concurrently applying different bias voltages to dummy memory cells and regular memory cells during erasure  
Integrated circuit flash memory devices, such as NAND flash memory devices, include an array of regular flash memory cells, an array of dummy flash memory cells and an erase controller. The erase...
8693248 Nonvolatile data storage devices, program methods thereof, and memory systems including the same  
Provided are methods of programming a nonvolatile data storage device including memory blocks sharing a block word line. The methods may include selecting the memory blocks, and the selected...
8665652 Method for erasing memory array  
A method for erasing a memory array is provided. The memory array comprises a plurality of memory cell strings, and each of the memory cell strings comprises a plurality of memory cells connected...
8654592 Memory devices with isolation structures  
Memory devices and methods of programming and forming the same are disclosed. In one embodiment, a memory device has memory cells contained within dielectric isolation structures to isolate them...
8654587 Nonvolatile memory devices, channel boosting methods thereof, programming methods thereof, and memory systems including the same  
Non-volatile memory device channel boosting methods in which at least two strings are connected to one bit line, the channel boosting methods including applying an initial channel voltage to...
8638611 Vertical nonvolatile memory devices and methods of operating same  
Integrated circuit memory devices include a plurality of vertically-stacked strings of nonvolatile memory cells having respective vertically-arranged channel regions therein electrically coupled...
8638606 Substrate bias during program of non-volatile storage  
A programming technique which reduces program disturb in a non-volatile storage system is disclosed. A positive voltage may be applied to a substrate (e.g., p-well) during programming. Biasing the...
8634252 Methods of operating a memory device having a buried boosting plate  
Memory devices are disclosed, such as those that include a semiconductor-on-insulator (SOI) NAND memory array having a boosting plate. The boosting plate may be disposed in an insulator layer of...
8625349 Potential relationship in an erasing operation of a nonvolatile semiconductor memory  
A memory includes a first word line which is connected to a control gate electrode of a first memory cell, a second word line which is connected to a control gate electrode of a second memory...
8619469 FTP memory device with programming and erasing based on Fowler-Nordheim effect  
An embodiment of a non-volatile memory device integrated in a chip of semiconductor material is proposed. The memory device includes a plurality of memory cells. Each memory cell includes a first...
8611148 Data state-dependent channel boosting to reduce channel-to-floating gate coupling in memory  
In a programming operation, selected storage elements on a selected word line are programmed while unselected storage elements on the selected word line are inhibited from programming by channel...