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7391639 Memory device and method for reading data  
A memory with memory cells, wherein a memory cell includes a resistive element and a switch, wherein the memory cells are connected with a common plate line and with respective bit lines, wherein...
7388790 Semiconductor memory device and dynamic latch refresh method thereof  
A semiconductor integrated circuit device includes dynamic latches, switch circuit, capacitor, first static latch, and first transfer gate. In refreshing data of the dynamic latches, data stored in...
7388789 NAND memory device and programming methods  
A NAND Flash memory device is described that can reduce circuitry noise during program operations. The memory includes bit lines that can be electrically coupled together to charge share their...
7385868 Method of refreshing a PCRAM memory device  
A method for refreshing PCRAM cells programmed to a low resistance state and entire arrays of PCRAM cells uses a simple refresh scheme which does not require separate control and application of...
7385855 Nonvolatile memory device having self reprogramming function  
A nonvolatile memory device having a self reprogramming function is provided. The nonvolatile memory device includes a memory cell, a first transistor, a second transistor, and a latch circuit. The...
7385848 Semiconductor storage device and electronic equipment  
A semiconductor storage device has a memory cell array composed of a plurality of arrayed memory cells, word lines, bit lines, a bit line charging and discharging circuit, and a readout section....
7382657 Semiconductor memory device having bit line precharge circuit controlled by address decoded signals  
A semiconductor memory device includes a memory cell array, a charge circuit which compensates for OFF leakage current developed at selected bit lines, a reset circuit having a ground potential...
7382651 Nonvolatile semiconductor memory device  
In a control order of non-selected blocks at the time of data erase operation of one or a plurality of blocks, the control gate line is controlled to ground potential at first, then subsequently, a...
7379346 Erase inhibit in non-volatile memories  
A non-volatile memory and method for its operation that can reduce the amount of disturb in non-selected cells during an erase process are presented. For a set of storage elements formed over a...
7379345 Nonvolatile semiconductor memory device that achieves speedup in read operation  
A plurality of first sub-bit lines are each connected to a common source line via a corresponding first sub-bit line reset transistor with NMOS structure, and a plurality of second sub-bit lines...
7379340 Sense amplifier circuit in non-volatile semiconductor memory comprising a boosting capacitor for boosting the potential at sense node  
A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to...
7376009 Semiconductor memory device which stores plural data in a cell  
A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n...
7372739 High voltage generation and regulation circuit in a memory device  
An auxiliary voltage generation circuit is part of a high voltage generation and regulation circuit. The auxiliary voltage generation circuit generates an auxiliary intermediate voltage that is...
7372738 Flash memory device with reduced erase time  
A NOR flash memory device comprises a memory cell array, a row selection circuit adapted to drive wordlines in the memory cell array with a wordline voltage during an erase operation, and an erase...
7372730 Method of reading NAND memory to compensate for coupling between storage elements  
A method for reading a non-volatile memory arranged in columns and rows which reduces adjacent cell coupling, sometimes referred to as the Yupin effect. The method includes the steps of: selecting...
7369450 Nonvolatile memory having latching sense amplifier and method of operation  
A memory comprises a sense amplifier for sensing a logic state of a selected bitline. The sense amplifier includes a first precharge circuit, a current-to-voltage converter, a latch circuit, and a...
7369442 Erase discharge method of memory device and discharge circuit performing the method  
A method for discharging an erase voltage of a semiconductor memory device and discharge circuit for performing the method, the method including performing a first discharge on a common source line...
7362617 Nonvolatile semiconductor memory device and method of rewriting data thereof  
The nonvolatile semiconductor memory device of the present invention includes a memory cell array wherein data is stored in a nonvolatile state based on a difference in memory information between...
7352618 Multi-level cell memory device and associated read method  
A NOR flash memory device comprises a memory cell adapted to store at least two bits of data. A read operation is performed on the memory cell by generating a reference current with a first...
7349265 Reading method of a NAND-type memory device and NAND-type memory device  
A reading method of a NAND memory device includes the steps of first connecting a first end terminal of a stack of cells to a reference line, second connecting a second end terminal of the stack of...
7345916 Method and apparatus for high voltage operation for a high performance semiconductor memory device  
A method and apparatus are provided for high performance, high voltage memory operations on selected memory cells ( 200 ) of a semiconductor memory device ( 100 ). A high voltage generator ( 106 )...
7342835 Memory device with pre-fetch circuit and pre-fetch method  
A memory device includes plural memory blocks, each memory block having memory cells arranged in wordlines and bitlines and a selector to select a wordline of memory cells. A group of first sense...
7342832 Bit line pre-settlement circuit and method for flash memory sensing scheme  
A flash memory array includes a reference bit line on which a reference current is imposed. During read operation, bit lines selected for reading are connected to current-to-voltage converters,...
7339833 Non-volatile semiconductor memory device  
Using charges accumulated in a capacitance element connected to a drain side node of a memory cell, data is written in accordance with source side injection method. The capacitance value of the...
7330377 Semiconductor memory device  
A semiconductor memory device has a driver including a first resistor, and a control signal generator including a second resistor. A storage unit is employed to store adjustment data for setting a...
7327615 Electric potential switching circuit, flash memory with electric potential switching circuit, and method of switching electric potential  
An electric potential switching circuit has an electric potential control circuit, an output circuit, and a precharge circuit connected to the output circuit. The electric potential control circuit...
7327610 DRAM memory with common pre-charger  
A memory layout where the pre-charger circuits are connected between different pairs of bit lines than are the sense amplifiers: The two bits lines in each bit line pair are connected to different...
7324385 Molecular memory  
Molecular memories, i.e., memories that incorporate molecules for charge storage, are disclosed. Molecular memory cells, molecular memory arrays, and electronic devices including molecular memory...
7324378 Method of driving a program operation in a nonvolatile semiconductor memory device  
In an embodiment, a method of driving a program operation in a nonvolatile semiconductor memory device is operable without discharging a bitline connected to a memory cell to be programmed between...
7321515 Memory device and control method therefor  
An access identification circuit ( 4 ) identifies a first access operation or a second access operation and outputs an identification signal S. During the first access operation, stored data is...
7319617 Small sector floating gate flash memory  
To control the problem of program and erase disturb in flash memory arrays having multiple sectors of cells grouped in each isolation wells of the flash memory array, a refresh procedure is used...
7313028 Method for operating page buffer of nonvolatile memory device  
A method for operating a page buffer of a nonvolatile memory device reduces errors while transferring data between latches and shortens a copy-back programming time. The copy-back program is...
7313018 Methods and apparatus for a non-volatile memory device with reduced program disturb  
A non-volatile memory device includes a plurality of power control circuits interfaced via a single Y multiplexer with an array of memory cells. The multiple power control circuits provide multiple...
7301819 ROM with a partitioned source line architecture  
A partitioned source line architecture for reducing leakage and power in a ROM. In one embodiment, a ROM is comprised of a plurality of storage cells organized as an array having M rows and N...
7298653 Reducing cross die variability in an EEPROM array  
In an EEPROM array the cells are pre-charged or pre-erased so that they will respond uniformly to the same read voltage level. By clearly defining the threshold voltage for the cells in their...
7295466 Use of recovery transistors during write operations to prevent disturbance of unselected cells  
A memory array and method for performing a write operation in a memory array that eliminates parasitic coupling between selected and unselected bitlines and protects memory cells on unselected...
7292474 Semiconductor integrated circuit device  
A semiconductor integrated circuit device has a memory cell array including a plurality of pages and a page buffer. Each of the plurality of pages includes a user region and a page flag region in...
7286407 Semiconductor device and method for controlling the same  
A semiconductor device includes a program voltage supply circuit that supplies a drain of a memory cell with a program voltage, and a pull-down circuit that pulls down a potential of an output of...
7280407 Semiconductor memory device including floating gates and control gates, control method for the same, and memory card including the same  
A semiconductor memory device includes memory cells, a memory cell array, word lines, a first charge pump circuit, and a discharge circuit. The memory cell has a first MOS transistor with a stacked...
7280395 Methods for neutralizing holes in tunnel oxides of floating-gate memory cells and devices  
Methods for neutralizing holes in tunnel oxides of floating-gate memory cells and devices using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a...
7277342 Semiconductor memory having dummy bit line precharge/discharge circuit  
Reset dummy cells which change the load capacitance of a dummy read line DRD according to stored information are provided. Memory information are set to the reset dummy cells according to...
7277339 Semiconductor storage device precharging/discharging bit line to read data from memory cell  
A read circuit includes a precharge circuit, a discharge circuit, and a sense amplifier. The precharge circuit includes a first transistor which has a gate connected to the bit line, a second...
7277327 Methods for erasing flash memory  
Methods for erasing flash memory using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a second polarity during an erase period.
7272065 Compensated refresh oscillator  
A method and apparatus is provided for implementing a refresh rate control scheme that is capable of compensating for external factors. Using a circuit, a change in a current leakage relating to at...
7272053 Integrated circuit having a non-volatile memory with discharge rate control and method therefor  
An integrated circuit includes a memory ( 10 ). The memory ( 10 ) includes an array ( 12 ) of non-volatile memory cells. Each memory cell ( 14 ) of the array ( 12 ) includes a plurality of...
7272044 Flash memory  
Flash memory supporting methods for erasing memory cells using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a second...
7266016 Electrically rewritable nonvolatile semiconductor memory device  
A clamp circuit is connected to one-side ends of first and second bit lines which are adjacent in a memory cell array and a data cache is connected to the other ends thereof. The first and second...
7263004 Method and apparatus for determining sensing timing of flash memory  
A method of automatically determining a sensing timing in a page buffer of a NAND flash memory device is disclosed, which includes the steps of discharging a first reference bit line, discharging a...
7263003 Two-transistor flash memory device using replica cell array to control the precharge/discharge and sense amplifier circuits of the primary cell array  
A semiconductor memory device includes a memory cell array, first bit lines, second bit lines, a first precharge circuit, a sense amplifier, and a read control circuit. The memory cell array has a...
7263001 Compact non-volatile memory cell and array system  
NVM arrays include rows and columns of NVM cells comprising a floating gate, a programming element, and a logic storage element. During a programming or erase mode, the floating gate of each cell...
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