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7372732 Pulse width converged method to control voltage threshold (Vt) distribution of a memory cell  
A method of operating on a plurality of non-volatile multi-level memory cells is disclosed. The memory cells have at least a first, second, third and fourth program level. Each of program levels...
7369440 Method, circuit and systems for erasing one or more non-volatile memory cells  
The present invention is a method, circuit and system for erasing one or more non-volatile memory (“NVM”) cells in an NVM array or array segment. According to some embodiments of the present...
7366022 Apparatus for programming of multi-state non-volatile memory using smart verify  
In a non-volatile memory, the initiation of program verification is adaptively set so that programming time is decreased. In one approach, non-volatile storage elements are programmed based on a...
7366020 Flash memory device capable of preventing an overerase of flash memory cells and erase method thereof  
We describe a NAND flash memory device including a memory cell array formed on a substrate including a plurality of cell strings each including a string selecting transistor, a ground selecting...
7362646 Semiconductor memory device  
A semiconductor memory device includes a memory cell array provided in a cell array area and including a plurality of memory cells, a source potential line which applies a source potential to the...
7362610 Programming method for non-volatile memory and non-volatile memory-based programmable logic device  
A method for programming a flash memory cell comprises providing input data to the flash cell and providing a segmented programming pulse to the flash memory cell. The segmented programming pulse...
7362617 Nonvolatile semiconductor memory device and method of rewriting data thereof  
The nonvolatile semiconductor memory device of the present invention includes a memory cell array wherein data is stored in a nonvolatile state based on a difference in memory information between...
7359239 Non-volatile memory device having uniform programming speed  
Flash memory devices having a cell string structure. According to the present invention, the size of a first group of memory cells connected to a first word line and a second group of memory cells...
7359248 Methods for programming and reading NAND flash memory device and page buffer performing the same  
Methods for programming and reading a multi-level-cell NAND flash memory device having plural memory cells are disclosed to reduce the programming time and the reading time. The program method...
7352631 Methods for programming a floating body nonvolatile memory  
A technique to speed up the programming of a non-volatile memory device that has a floating body actively removes holes from the floating body that have accumulated after performing hot carrier...
7345913 Semiconductor memory device  
A semiconductor memory device, comprising: a memory cell array of a plurality of memory cell units, each memory cell unit including a plurality of serially connected memory cells formed on the same...
7345921 Method and system for a programming approach for a nonvolatile electronic device  
Aspects for programming a nonvolatile electronic device include performing an initial verify step of a programming algorithm with an initial type of reference voltage value, and performing one or...
7345922 Position based erase verification levels in a flash memory device  
The location of a cell to be erase verified is determined. The erase verification threshold voltage is then set. The threshold voltage is changed in response to the cell's location with respect to...
7345918 Selective threshold voltage verification and compaction  
Non-volatile memory devices for providing selective compaction verification and/or selective compaction to facilitate a tightening of the distribution of threshold voltages in memory devices...
7339823 Nonvolatile semiconductor storage apparatus and method of driving the same  
A memory cell array is logically divided into a plurality of regions having different reading speeds, the respective regions having the different reading speeds include region information storage...
7339826 Threshold voltage shift in NROM cells  
An NROM (nitride read only memory) cell, which is programmed by channel hot electron injection and erased by hot hole injection, includes a charge trapping structure formed of: a bottom oxide...
RE40110 Nonvolatile semiconductor memory device for storing multivalued data  
A multivalued memory has data of state “0”, state “1”, state “2”, and state “3” whose threshold voltages increase in that order. In a first-page write operation, a memory cell whose...
7336540 Indirect measurement of negative margin voltages in endurance testing of EEPROM cells  
An electronic test structure and method for testing non-volatile memory cells. The structure includes a first transistor coupled in series to a floating gate transistor whereby a source of the...
7336539 Method of operating flash memory cell  
A flash memory cell is provided. A deep well is disposed in a substrate and a well is disposed within the deep well. A stacked gate structure is disposed on the substrate. A source region and a...
7330374 Nonvolatile semiconductor memory device, such as an EEPROM or a flash memory, with reference cells  
To set a threshold of a reference cell in short time in a semiconductor memory device using a variable threshold type nonvolatile memory cell as a reference current/voltage generating unit, a...
7330376 Method for memory data storage by partition into narrower threshold voltage distribution regions  
A method for data storage of a memory unit and a memory unit using the same are provided in the present invention. The method for data storage of a memory unit includes: first, dividing a memory...
7324375 Multi-bits storage memory  
A nonvolatile memory apparatus including a control circuit, plural terminals having clock, command and other terminals, data and command registers, and plural nonvolatile memory cells. The clock...
7315475 Non-volatile semiconductor memory device  
A sense amplifier has first and second input nodes. A reference memory cell is connected to the first input node. To the second input node, a constant current source circuit and a main memory cell...
7310347 States encoding in multi-bit flash cells  
N data bits are stored in ┌N/M┐ cells by programming each cell with up to M of the bits according to a valid, nonserial bit ordering that satisfies one of the following criteria: Either the...
7310255 Non-volatile memory with improved program-verify operations  
In programming a non-volatile memory involving alternately applying a programming pulse and verifying the programming, time is saved in the program verify portion when, depending on the states of...
7308067 Read bias scheme for phase change memories  
A read bias scheme may be used for phase change memories including a chalcogenide access device and a chalcogenide memory element. Through an appropriate read bias scheme, desirable read margin can...
7304896 Method and circuit for simultaneously programming memory cells  
A method for simultaneously programming a pre-established number of memory cells includes setting an initial number of memory cells to be simultaneously programmed equal to the pre-established...
7305513 Circuit for preventing nonvolatile memory from over-erase  
A method for preventing the over-erase in a nonvolatile memory comprises the following steps. First, at least one normal cell of the nonvolatile memory and at least one reference cell that...
7301818 Hole annealing methods of non-volatile memory cells  
Hole annealing methods are described after erasure of nitride storage memory cells for compensating trapped holes to minimize the holes from detrapping in order to reduce the amount of threshold...
7301815 Semiconductor memory device comprising controllable threshould voltage dummy memory cells  
The present invention provides a semiconductor memory device capable of preventing a defect caused by falling of a word line and deterioration in patterning precision due to disturbance of the...
7295474 Operating an information storage cell array  
A cell in an information storage cell array is written, by asserting a signal on a bit line that is coupled to the cell and to a group of other cells in the array, to a first voltage. The cell is...
7292473 Method and apparatus for programming/erasing a non-volatile memory  
A non-volatile memory (NVM) that can be optimized for data retention or endurance is divided into portions that are optimized for one or the other or potentially some other storage characteristic....
7289371 Semiconductor memory device and electronic equipment  
A semiconductor memory device has a memory cell array in which a plurality of nonvolatile memory cells are arranged. The memory device also has word lines, bit lines connected with the memory cells...
7286410 Semiconductor integrated circuit  
A semiconductor integrated circuit has a first nonvolatile memory area and a second nonvolatile memory area to store information in accordance with a variable threshold voltage. At least one...
7286381 Non-volatile and-type content addressable memory  
In order to speed up the search for a data item in a content addressable memory and to simplify the circuit structure of the memory having associated with each row of cells a ground control line, a...
7286412 Method and apparatus to improve nonvolatile memory data retention  
Disclosed are apparatuses, methods, and manufacturing methods relating to improving data retention in nonvolatile memory. In many embodiments, monitor reference currents in addition to a normal...
7286403 Non-volatile semiconductor memory device  
According to one embodiment of this invention, a non-volatile semiconductor memory device of high speed program operation is realized. It provides a non-volatile semiconductor memory device...
7283397 Flash EEprom system capable of selective erasing and parallel programming/verifying memory cell blocks  
A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. A chunk of user data is programmed into a group of...
7280402 Method for reading flash memory cell, NAND-type flash memory apparatus, and NOR-type flash memory apparatus  
A method of reading a flash memory cell, a NAND-type flash memory apparatus, and/or a NOR-type flash memory apparatus improves the resolution capability and reduces the determination time by using...
7280413 Nonvolatile semiconductor memory  
A transmission transistor transmitting a drain voltage is connected to an electrically rewritable nonvolatile memory cell. An operation control circuit controls program operation for increasing a...
7280395 Methods for neutralizing holes in tunnel oxides of floating-gate memory cells and devices  
Methods for neutralizing holes in tunnel oxides of floating-gate memory cells and devices using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a...
7274599 NOR flash memory device using bit scan method and related programming method  
A NOR flash memory device configured to perform a program operation using an ISPP scheme, and comprising a plurality of memory cells, a word line voltage generator, and a scan controller is...
7274600 NAND flash memory with read and verification threshold uniformity  
A plurality of cells in a flash memory device are coupled together in a series configuration, as in a NAND flash memory. A position of a first accessed cell is determined with reference to a ground...
7272065 Compensated refresh oscillator  
A method and apparatus is provided for implementing a refresh rate control scheme that is capable of compensating for external factors. Using a circuit, a change in a current leakage relating to at...
7272044 Flash memory  
Flash memory supporting methods for erasing memory cells using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a second...
7272050 Non-volatile memory device and erase method of the same  
An erase method of a non-volatile memory device including memory cells arranged in a matrix of rows and columns. The memory cells are erased at the same time. An erase-verify operation is performed...
7269067 Programming a memory device  
A method of programming a memory cell in a non-volatile memory device includes applying a first voltage to a control gate associated with the memory cell and applying a second voltage to a drain...
7266017 Method for selective erasing and parallel programming/verifying of cell blocks in a flash EEprom system  
A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. A chunk of user data is programmed into a group of...
7262999 System and method for preventing read margin degradation for a memory array  
An ultra cycling nitride read only memory (NROM) device is coupled to a NROM array such that both bits of the ultra cycling NROM device will be erased when all NROM devices of the NROM array are...
7259995 Memory device  
A method of stabilizing a memory device comprises trapping a plurality of electric charges in a charge trapping layer of the memory device. The charge trapping layer is positioned between a...
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