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6643177 Method for improving read margin in a flash memory device  
A method for providing a modified threshold voltage distribution for a dynamic reference array in a flash memory cell array. The dynamic reference array and an associated core memory cell array are...
6639839 Sensing method for EEPROM refresh scheme  
A method for determining the necessity for refreshing memory cells of a flash memory that includes providing a first reference memory cell, measuring a current of the first reference memory cell,...
6639849 Nonvolatile semiconductor memory device programming second dynamic reference cell according to threshold value of first dynamic reference cell  
In a nonvolatile semiconductor memory device, first and second dynamic reference cells are subjected to a same rewriting operation as performed to a memory cell. An average reference current is...
6636440 Method for operation of an EEPROM array, including refresh thereof  
A method for operating an electrically erasable programmable read only memory (EEPROM) array, the method including refreshing a threshold voltage of a bit of a memory cell in an EEPROM array, the...
6633499 Method for reducing voltage drops in symmetric array architectures  
A symmetric segmented array has select transistors and column select transistors. At least one of the select and/or column select transistors is a low threshold voltage device. Alternatively, at...
6621742 System for programming a flash memory device  
System to program core cells in a memory device without over-programming. The system includes a method for programming a voltage threshold (Vt) level of a core cell in a memory device. The method...
6621740 Non-volatile semiconductor memory device  
A specific row of memory cells in a flash memory is set to be in a lock mode state, which affects reading of data in other rows of memory cells in a common memory array. Thus, a flash memory having...
6618286 Non-volatile semiconductor memory device with a memory array preventing generation of a through current path  
A NROM(R) memory array is divided into memory blocks. An isolating portion for electrically isolating corresponding memory blocks from each other is formed in the boundary region between adjacent...
6614694 Erase scheme for non-volatile memory  
A method of an erase scheme for a non-volatile memory cell. The non-volatile memory cell includes a substrate, source, drain with a channel region and a gate above the channel region separated by...
6608499 Method for compensating a threshold voltage of a neighbor bit  
A method for compensating a threshold voltage of a neighbor bit, are provided. The method includes the first step of arbitrating the word line voltages applied to bits demanded to be programmed,...
6606266 Nonvolatile semiconductor memory device capable of writing multilevel data at high rate  
A program data latch circuit supplies one of a write bit line potential and a write prohibiting potential corresponding to multilevel data to be written, to a bit line in accordance with a level of...
6606273 Methods and systems for flash memory tunnel oxide reliability testing  
Methods are disclosed for determining tunnel oxide reliability of flash memory devices in a wafer prior to sorting and packaging without damaging or stressing the devices. The methods comprise...
6603679 Coupling coefficient measuring method and coupling coefficient measuring apparatus for semiconductor memory  
A coupling coefficient measuring method for a semiconductor memory capable of directly measuring a coupling coefficient in an actual cell without employing a specific test structure including a...
6597606 Charging a capacitance of a memory cell and charger  
The present invention is in the field of charging a capacitance of a memory cell. Embodiments of the present invention program a memory cell by determining programming pulses to be used to program...
6597604 Flash memory cell array and method for programming and erasing data using the same  
A flash memory cell array and a method for programming and erasing data using the same are provided, in which problems related to over-erasing and disturbance are overcome and a cell area per bit...
6587903 Soft programming for recovery of overerasure  
A method of erasing a memory cell includes the step of erasing a memory cell. The current in the memory cell is measured. If the measured memory cell current approximately exceeds a predetermined...
6587377 Nonvolatile semiconductor memory device with reliable verify operation  
A nonvolatile semiconductor memory device includes a reference circuit which includes a plurality of reference cell transistors connected together and receiving a common gate voltage, and includes...
6580640 Non-volatile memory device with tunnel oxide  
A method and apparatus invention that relates to the reduction of leakage current through a tunnel oxide layer of a memory cell to improve data retention. One method of operating a non-volatile...
6580632 Semiconductor memory device, method for driving the same and method for fabricating the same  
Data is read out from a ferroelectric film with its remnant polarization associated with one of two possible logical states of the data and with a bias voltage applied to a control gate electrode...
6577539 Non-volatile semiconductor memory device with programming voltage generating system and data programming method  
On a non-volatile semiconductor memory, a large current can be flowed through the memory cell during reading. The number of the column lines can be reduced. The electron injection to the floating...
6574158 Method and system for measuring threshold of EPROM cells  
An approach for testing an erasable programmable read-only memory (EPROM) cell for a threshold voltage is provided. A voltage lower than a source voltage that is associated with a read operation is...
6574139 Method and device for reading dual bit memory cells using multiple reference cells with two side read  
A method for reading at least one programmed dual bit memory cell using a plurality of programmed dual bit reference cells. The reference cells are programmed with selected parameters to compensate...
6567302 Method and apparatus for programming multi-state cells in a memory device  
A method for programming multi-state floating gate transistor memory cells, also called multi-state flash cells, in a memory system is disclosed. The memory system includes control circuitry for...
6556477 Integrated chip having SRAM, DRAM and flash memory and method for fabricating the same  
A semiconductor memory system fabricated on one substrate is presented including an SRAM device, a DRAM device and a Flash memory device. In one embodiment the SRAM device is a high-resistive load...
6556481 3-step write operation nonvolatile semiconductor one-transistor, nor-type flash EEPROM memory cell  
In the present invention a three step write of a nonvolatile single transistor cell is disclosed. The three steps comprise erasing, reverse programming and programming which can be applied to a...
6549466 Using a negative gate erase voltage applied in steps of decreasing amounts to reduce erase time for a non-volatile memory cell with an oxide-nitride-oxide (ONO) structure  
An erase operation is performed on a non-volatile memory cell with an oxide-nitride-oxide structure by using a negative gate erase voltage during an erase procedure to improve the speed and...
6545912 Erase verify mode to evaluate negative Vt's  
A method is provided to determine erase threshold voltages of memory transistors and thereby identify unusable memory transistors. A voltage is applied to the common source of a selected memory...
6545525 Semiconductor device including interface circuit, logic circuit, and static memory array having transistors of various threshold voltages and being supplied with various supply voltages  
The well voltage of a CMOS circuit having low-threshold-voltage MOSFETs is controlled when the power supply is turned on, during normal operation, and when the supply voltage is cut off. The CMOS...
6535432 Method of erasing a non-volatile memory  
A method of erasing a non-volatile memory. The non-volatile memory is positioned on a substrate of a semiconductor wafer and has a memory array region. The memory array region has memory cells,...
6535423 Drain bias for non-volatile memory  
An apparatus and method are disclosed for providing drain bias for non-volatile memory. According to one embodiment, the drain bias is provided utilizing a drain bias circuit that is referenced by...
6529414 Nonvolatile semiconductor memory device including a circuit for providing a boosted potential  
In a flash memory EEPROM, a memory cell MC is formed in a P-type semiconductor substrate. A peripheral transistor TR is formed in an N-type well. Another peripheral transistor TR is formed in a...
6525965 One-sided floating-gate memory cell  
Floating-gate memory cells having a control gate for coupling to a word line, a floating gate, a first source/drain region for coupling to a bit line, and a floating second source/drain region are...
6519184 Non-volatile memory device with plurality of threshold voltage distributions  
In a verify operation after a write or erase to check whether a memory cell threshold voltage is contained in a predetermined threshold voltage distribution, verify voltage is changed in three...
6515908 Nonvolatile semiconductor memory device having reduced erase time and method of erasing data of the same  
Erasing is performed two times for narrowing a distribution width of threshold voltages of memory cells, and reducing the number of memory transistors to be subjected to over-erase verify. The...
6515907 Complementary non-volatile memory circuit  
A non-volatile memory circuit has FLOTOX type memory elements operable with a low data writing voltage even when a difference between threshold voltages of non-volatile memory elements is small....
6510083 Electrically erasable and programmable memory that allows data update without prior erasure of the memory  
A processor-implemented method is described for updating a datum stored in a nonvolatile memory, bits of which cannot be overwritten from a first logical state to a second logical state without a...
6498757 Structure to inspect high/low of memory cell threshold voltage using current mode sense amplifier  
A structure to inspect high/low of memory cell threshold voltage using a current mode sense amplifier. A current mode sense amplifier is used to compare a memory cell current of a selected memory...
6496418 Semiconductor integrated circuit and data processing system  
A control of a flash memory includes control for supplying a pulse-shaped voltage to each of non-volatile memory cells until a threshold voltage of the non-volatile memory cell having a first...
6493266 Soft program and soft program verify of the core cells in flash memory array  
A method and system are disclosed for memory cell soft program and soft program verify, to adjust, or correct the threshold voltage between a target minimum and maximum, which may be employed in...
6493265 Nonvolatile semiconductor memory device  
A method of determining multi-bit data in a multi-level memory. The method includes setting a source potential of a memory cell to a first source potential, setting a gate potential thereof to a...
6487121 Method of programming a non-volatile memory cell using a vertical electric field  
A method of programming a memory cell with a substrate that includes a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that...
6487114 Method of reading two-bit memories of NROM cell  
A method of reading two-bit information in Nitride Read only memory (NROM) cell simultaneously. According to outputted voltage in drain or source of the NROM, it can identify a logical two-bit...
6477084 NROM cell with improved programming, erasing and cycling  
A nitride programmable read only memory (NROM) cell with a pocket implant self-aligned to at least one bit line junction. Alternatively, the bit line junction(s) can have a thin area of effective...
6476441 Method and structure for textured surfaces in floating gate tunneling oxide devices  
A method and structure for textured surfaces in non volatile floating gate tunneling oxide (FLOTOX) devices, e.g. FLOTOX transistors, are provided. The present invention capitalizes on using...
6466480 Method and apparatus for trimming non-volatile memory cells  
A method and apparatus for trimming a non-volatile memory cell. One method comprising, erasing the memory cell below a desired voltage threshold (Vt) level, applying a program pulse to the memory...
6462372 Scaled stack-gate flash memory device  
A stack-gate structure including a masking dielectric layer over a control-gate layer over an intergate dielectric layer over a floating-gate layer formed on a gate-dielectric layer is formed on a...
6459620 Sense amplifier offset cancellation in non-volatile memory circuits by dedicated programmed reference non-volatile memory cells  
A non-volatile memory (NVM) system including an array of NVM cells, a column decoder, a set of comparators and a corresponding set of NVM reference blocks is provided. During a read operation, the...
6456532 Semiconductor memory device  
The present invention is intended to provide a semiconductor memory circuit that can store analog and many-valued data at high speed and with a high degree of accuracy. The semiconductor memory...
6456536 Method of programming a non-volatile memory cell using a substrate bias  
A method of programming a memory cell with a substrate that includes a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that...
6456531 Method of drain avalanche programming of a non-volatile memory cell  
A method of programming a memory cell with a substrate that includes a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that...
Matches 451 - 500 out of 779 < 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 >