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7643340 Method and apparatus for programming multi level cell flash memory device  
A method of programming a selected cell in a multi-level flash memory device comprises determining whether to program an upper bit or a lower bit of a selected memory cell, detecting a current...
7643358 Non volatile semiconductor memory device  
A non volatile semiconductor memory device wherein it is possible to transfer Vpp without a drop in voltage of the transfer transistor Vth (threshold voltage) in a transfer circuit or decoder...
7643346 NAND type nonvolatile semiconductor memory device having sideface electrode shared by memory cells  
An electrically erasable programmable read-only memory (EEPROM) device of the NAND type having sideface electrodes as auxiliary electrodes on the opposite lateral surfaces of a transistor channel...
7639540 Non-volatile semiconductor memory having multiple external power supplies  
A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory. Additionally,...
7639555 Test circuit device for semiconductor memory apparatus  
A test circuit device for a semiconductor memory device includes a main word line driving unit that generates a signal that swings between a driving voltage and one of a first voltage and a second...
7636254 Wordline booster circuit and method of operating a wordline booster circuit  
The invention relates to a wordline booster circuit, especially an SRAM-wordline booster circuit, comprising a driving element ( 20 ) for shifting a voltage level of a charge storage element ( 50 )...
7636259 Flash memory array with independently erasable sectors  
Systems and methods are disclosed herein to provide a flash memory array with independently erasable sectors. For example, in accordance with an embodiment of the present invention, an integrated...
7633804 Adjusting programming or erase voltage pulses in response to the number of programming or erase failures  
Memory devices and methods of operating memory devices are provided. In one such embodiment a programming voltage pulse or an erase voltage pulse is applied to memory cells of a memory device. A...
7633806 Memory device with a nonvolatile memory array  
A memory device having a nonvolatile memory array, at least one driver for programming the memory array, which driver is connected to the memory array in order to drive a programming potential, and...
7630261 Nand-structured flash memory  
A NAND-structured flash memory including a selection transistor having a first conducting path, one end of the first conducting path being connected to a bit line or a source line, at least one...
7630226 Semiconductor device  
A memory cell includes: an irreversible storage element that writes data by breaking down an insulating film, with a write voltage being applied to its one end; and first and second transistors...
7630242 Nonvolatile semiconductor memory device  
With this flash memory, because a plurality of memory blocks are formed on a surface of a single P-type well, a layout area can be made small. Further, when erasing data for a memory block to be...
7630250 Controlled ramp rates for metal bitlines during write operations from high voltage driver for memory applications  
Systems and methods that control the switching transition times or profile of a ramped voltage write signal used for programming or erasing at least a wordline of an array of multi-bit and/or...
RE41020 Multi-state EEPROM having write-verify control circuit  
An EEPROM having a memory cell array in which electrically programmable memory cells are arranged in a matrix and each of the memory cells has three storage states, includes a plurality of data...
7623389 System for low voltage programming of non-volatile memory cells  
System for programming a selected non-volatile memory cell in a memory array having a gate node coupled to a wordline WL(n) and a drain node connected to a selected bitline by injecting hot...
7616512 Semiconductor memory device with hierarchical bit line structure  
A semiconductor memory device has a hierarchical bit line structure. The semiconductor memory device may include first and second memory cell clusters, which share the same bit line pair and are...
7616481 Memories with alternate sensing techniques  
The present invention presents a scheme for sensing memory cells. Selected memory cells are discharged through their channels to ground and then have a voltage level placed on the traditional...
7616487 Decoders and decoding methods for nonvolatile semiconductor memory devices  
A decoder for a non-volatile semiconductor memory device includes a level shifter configured to generate a negative first voltage at an output thereof responsive to a first state of a global word...
7613047 Efficient circuit and method to measure resistance thresholds  
The embodiments of the invention provide an apparatus, method, etc. for an efficient circuit and method to measure resistance. A sense line driver for an integrated circuit memory is provided,...
7613030 Semiconductor memory device and method for operating the same  
A semiconductor memory device is provided, which comprises an analog switch, a first inverter, a second inverter, and a clocked inverter. A first terminal of the analog switch is electrically...
7609559 Word line drivers having a low pass filter circuit in non-volatile memory device  
A word line driver system that utilizes a voltage selection circuit to supply one of several voltages to an output node coupled to a plurality of word line control circuits. Each word line control...
7609554 High voltage switching circuit  
A high voltage switching circuit that has a depletion mode NMOS transistor, an enhancement mode PMOS transistor and, an enhancement mode NMOS transistor. A control circuit generates first and...
7609558 Non-volatile semiconductor memory device  
A non-volatile semiconductor memory device includes a memory cell array having a plurality of multi-level memory cells connected in series. The plurality of multi-level memory cells forms a...
7606104 Semiconductor memory device and electric power supply method  
A semiconductor device includes a first and a second memory cell array each including a plurality of electrically reprogrammable memory cells arranged in the form of a matrix, the first memory cell...
7606070 Systems for margined neighbor reading for non-volatile memory read operations including coupling compensation  
Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge...
7606086 Nonvolatile semiconductor memory device  
A nonvolatile semiconductor memory device comprises a memory cell array in which memory cells are arranged in a row and column direction, a circuit for applying a first voltage to a selected bit...
7602651 Semiconductor integrated circuit device  
This disclosure concerns a device outputting data to the outside comprising a first transistor with a first conductive type which is connected between an output low voltage corresponding to a first...
7599243 Sense amplifier over driver control circuit and method for controlling sense amplifier of semiconductor device  
A semiconductor memory device includes a bit line sense amplifying block that senses and amplifies bit line data. A first driving block drives a pull up power line of the bit line sense amplifying...
7599226 Memory circuit, drive circuit for a memory and method for writing write data into a memory  
A first and second non-volatile memory transistor each have a floating gate electrode and a gate terminal. A first switch is connected between a first drain terminal and a bit line for reading out...
7596033 Nonvolatile semiconductor memory device  
A sub-decoder element provided corresponding to each word line is constructed by the same conductive type MOS transistors. The sub-decoder elements are arranged in a plurality of columns such that...
7596036 Memory control circuit, microcomputer, and data rewriting method  
A memory control circuit according to an embodiment of the present invention includes: a writable/readable memory; a comparison unit comparing write data to write in the memory with read data that...
7593249 Memory device for protecting memory cells during programming  
Improved circuitry and methods for programming memory cells of a memory device are disclosed. The improved circuitry and methods operate to protect the memory cells from potentially damaging...
7586787 Reducing bit line leakage current in non-volatile memories  
In example embodiments, methods are provided for reducing bit line leakage current. In an example embodiment, an unselected program word line is biased to a bias voltage. The unselected program...
7583539 Non-volatile storage with bias for temperature compensation  
A non-volatile storage system in which a body bias is applied to a non-volatile storage system to compensate for temperature-dependent variations in threshold voltage, sub-threshold slope,...
7580290 Non-volatile storage system with intelligent control of program pulse duration  
To program a set of non-volatile storage elements, a set of programming pulses are applied to the control gates (or other terminals) of the non-volatile storage elements. The programming pulses...
7580322 High speed programming for nonvolatile memory  
A nonvolatile memory device is programmed by selectively scanning input data bits to detect data bits to be programmed, and programming the detected data bits. The detected data bits may be...
7580288 Multi-level voltage adjustment  
An adjustable voltage supply ( 310 ) may have a plurality of levels of adjustment, such as a coarse select circuit ( 471 ) and a fine select circuit ( 473 ), to generate an adjustable voltage (e.g....
7577054 Memory with word-line driver circuit having leakage prevention transistor  
In a semiconductor memory having a plurality of word lines and bit lines and memory cells arranged at the positions of intersection thereof, a word driver circuit that drives the word line has a...
7567458 Flash memory array having control/decode circuitry for disabling top gates of defective memory cells  
A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high...
7564717 Semiconductor memory device  
A semiconductor memory device includes a memory cell array, word lines each of which connects the control gates of the memory cells on the same row together in the memory cell array, a row decoder...
7561475 Flash memory controller  
An apparatus for controlling a flash memory device which includes a signal generator for generating a clock signal at an operation, a first buffer for outputting the clock signal to the flash...
7561469 Programming method to reduce word line to word line breakdown for NAND flash  
A NAND architecture non-volatile memory device and programming process programs the various cells of strings of non-volatile memory cells by the application of differing word line pass voltages...
7561473 System for performing data pattern sensitivity compensation using different voltage  
Errors can occur when reading the threshold voltage of a programmed non-volatile storage element due to at least two mechanisms: (1) capacitive coupling between neighboring floating gates and (2)...
7558116 Regulation of boost-strap node ramp rate using capacitance to counter parasitic elements in channel  
Systems and/or methods that facilitate accessing data in a memory are presented. The memory can be flash memory that includes a plurality of sectors in an array that can be associated with a...
7558141 Memory system, semiconductor memory device and method of driving same  
A semiconductor memory device has a semiconductor substrate, first select transistors formed on the surface of said semiconductor substrate, first dummy transistors formed above said first select...
7558122 Flash memory device and method of erasing flash memory device  
A flash memory device and a method of erasing memory cells in a flash memory device are provided. A first post program operation is performed on erased memory cells having a threshold voltage lower...
7558152 Address counter for nonvolatile memory device  
An address counter for a nonvolatile memory device includes a cascade of cells. Each cell includes an address counting flip-flop that is updated to a value of every newly counted address bit, or...
7554847 Flash memory device employing disturbance monitoring scheme  
A flash memory device comprises a memory cell array including a plurality of NAND strings respectively connected to a plurality of bit lines, and further comprising a disturbed string coupled to a...
7551489 Multi-level memory cell sensing  
A multi-level cell memory device performs a read by providing a stepped voltage waveform on a wordline, and comparing cell currents to a substantially constant reference current. Prior to the...
7551487 Nonvolatile memory device and related programming method  
In a nonvolatile memory device, a first verification result indicates whether a block of memory cells has been successfully programmed and a second verification result indicates whether a far cell...
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