Matches 351 - 400 out of 1794 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >
Match Document Document Title
7428173 Low power NROM memory devices  
A buried bipolar junction is provided in a charge trapping transistor memory device. During a write operation electrons are injected into a surface depletion region of the memory cell transistors....
7426138 Parallel programming of multiple-bit-per-cell memory cells by controlling program pulsewidth and programming voltage  
Write operations that simultaneously program multiple memory cells on the same word line in an MBPC Flash memory employ word line voltage variation, programming pulse width variation, and...
7423913 Structures and methods for enhancing erase uniformity in a nitride read-only memory array  
A virtual ground nitride read-only memory array has a matrix of nitride read-only memory cells in which during an erase operation the non-erasing side of nitride read-only memory cells are...
7423908 Nonvolatile memory devices and methods of controlling the wordline voltage of the same  
A nonvolatile memory device includes an array of memory cells arranged in rows and columns, the array of memory cells having wordlines associated therewith. A wordline voltage controller determines...
7420856 Methods and circuits for generating a high voltage and related semiconductor memory devices  
Methods of generating a program voltage for programming a non-volatile memory device include generating an initial voltage and generating a first ramping voltage in response to the initial voltage....
7420852 Non-volatile memory device providing controlled bulk voltage during programming operations  
Disclosed is a non-volatile memory device and a method of programming the same. The non-volatile memory device comprises a plurality of memory cells that are programmed by supplying first and...
7417904 Adaptive gate voltage regulation  
A memory device generates a select voltage and an unselect voltage on bit lines and generates a bit line select voltage having a magnitude less than the unselect voltage so that the application of...
7417897 Method for reading a single-poly single-transistor non-volatile memory cell  
A method for operating a single-poly, single-transistor (1-T) non-volatile memory (NVM) cell. The NVM cell includes a gate on a P substrate, a gate dielectric layer, an N drain region and an N...
7414889 Structure and method of sub-gate and architectures employing bandgap engineered SONOS devices  
A bandgap engineered SONOS device structure for design with various AND architectures to perform a source side injection programming method. The BE-SONOS device structure comprises a spacer oxide...
7414891 Erase verify method for NAND-type flash memories  
An erase-verify method for a NAND flash memory includes a serial double-step erase verify. A verify operation is performed on cells in the unit connected to even word lines by biasing all the even...
7411827 Boosting to control programming of non-volatile memory  
Boosting signals are applied to unselected word lines for a set of NAND strings while a program voltage signal is applied to a selected word line. For a selected NAND string, in a first interval,...
7411831 Disk processing apparatus with voltage generating circuit having a boost ratio control  
The present invention is directed to largely reduce peak current at the time of operation of a boosting circuit provided for an EEPROM. In the erase/write operation, first, a low-frequency clock...
7411835 Discharge circuit for a capacitive load  
A circuit arrangement for the defined discharge of a capacitive load includes a first connecting terminal for connection of the load, a second connecting terminal for application of a predetermined...
7411828 Method and apparatus for programming single-poly pFET-based nonvolatile memory cells  
Methods and apparatuses for programming a single-poly pFET-based nonvolatile memory cell bias the cell so that band-to-band tunneling (BTBT) is induced and electrons generated by the BTBT are...
7411834 Nonvolatile semiconductor memory device  
A sub-decoder element provided corresponding to each word line is constructed by the same conductive type MOS transistors. The sub-decoder elements are arranged in a plurality of columns such that...
7411838 Semiconductor memory device  
A drive circuit 22 controls voltages applied to a substrate 1 , selection gates SG 0 and SG 1 , a local bit line LB 2 , and a control gate CGn. By respectively applying a negative voltage to...
7411830 Nonvolatile memory cell having current compensated for temperature dependency and data read method thereof  
A nonvolatile semiconductor memory device includes a memory cell array, read circuit, program circuit, read voltage generating circuit, memory circuit and switching circuit. The read voltage...
7411836 Method of operating non-volatile memory  
A method of operating a non-volatile memory comprising a substrate, a gate, a charge-trapping layer, a source region and a drain region is provided. The charge-trapping layer close to the source...
7411821 Method and apparatus to protect nonvolatile memory from viruses  
An apparatus, system, method, and article for protecting nonvolatile memory from viruses are described. The apparatus may include a nonvolatile memory comprising one or more protected storage...
7408820 Nonvolatile semiconductor memory with virtual ground array  
A nonvolatile semiconductor memory of virtual ground array in which a common connection of the sources and a common connection of the drains of nonvolatile memory cells arranged in rows and columns...
7408807 NAND string wordline delay reduction  
An improved NAND Flash memory and word line selection method has been described, that takes advantage of the asymmetric nature of the word line to word line capacitive coupling to reduce word line...
7408810 Minimizing effects of program disturb in a memory device  
A selected word line that is coupled to cells for programming is biased with an initial programming voltage. The unselected wordlines that are adjacent to the selected word line are biased at an...
7408811 NAND-type flash memory on an SOI substrate with a carrier discharging operation  
A semiconductor memory device includes: a semiconductor layer provided on an insulating substrate or an insulating layer; active areas each defined in the semiconductor layer with a device...
7405968 Non-volatile memory cell using high-K material and inter-gate programming  
A non-volatile memory device has a channel region between source/drain regions, a floating gate, a control gate, a first dielectric region between the channel region and the floating gate, and a...
7405977 Flash memory device with improved read speed  
A flash memory device comprises an array of memory cells arranged in rows and columns and a word line voltage generating circuit adapted to generate a plurality of read voltages at the same time...
7405972 Non-volatile memory array  
A non-volatile memory array including a plurality of memory units is provided. Each memory unit is serially connected with a select transistor and a memory cell. A source region is next to the...
7405979 Nonvolatile memory system, semiconductor memory, and writing method  
A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing...
7403428 Systems for erasing non-volatile memory utilizing changing word line conditions to compensate for slower erasing memory cells  
Voltage conditions applied to the memory cells of a non-volatile memory system are changed during erase operations in order to equalize the erase behavior of the select memory cells with other...
7403420 Flash memory device and associated recharge method  
A flash memory device comprises first and second mat structures connected to respective first and second high voltage lines, and a switch circuit connected between the first and second high voltage...
7403418 Word line voltage boosting circuit and a memory array incorporating same  
A first embodiment of a word line voltage boosting circuit for use with an array of non-volatile memory cells has a capacitor, having two ends, connected to the word line. One end of the capacitor...
7403434 System for controlling voltage in non-volatile memory systems  
System for a non-volatile memory system is provided. The non-volatile memory system includes a voltage generator system operating in one of a plurality of modes for generating a voltage applied to...
7400532 Programming method to reduce gate coupling interference for non-volatile memory  
A non-volatile memory device and programming process is described that compensates for coupling effects on threshold gate voltages of adjacent floating gate or non-conductive floating node memory...
7400527 Bit symbol recognition method and structure for multiple bit storage in non-volatile memories  
Storage of information represented by a multi-bit word in a single non-volatile memory cell is made possible by programming the threshold voltage of the non-volatile memory to a specific threshold...
7400533 Mimicking program verify drain resistance in a memory device  
A selected word line is biased with a program verify voltage. A predetermined quantity of unselected word lines that are between the selected word line and the bit line are biased with a modified V...
7400537 Systems for erasing non-volatile memory using individual verification and additional erasing of subsets of memory cells  
A set of non-volatile storage elements is divided into subsets for erasing in order to avoid over-erasing faster erasing storage elements. The entire set of elements is erased until a first subset...
7397699 Channel discharging after erasing flash memory devices  
A post-erase channel clearing procedure for double well, floating gate, non-volatile memory cells. The channel is cleared of charged particles coming from the floating gate after an erase operation...
7397700 Non-volatile memory electronic device with NAND structure being monolithically integrated on semiconductor  
A non-volatile memory electronic device is integrated on a semiconductor and is of the Flash EEPROM type with an architecture of the NAND type including at least one memory matrix organized in rows...
7397701 Method and apparatus for operating a string of charge trapping memory cells  
An array of charge trapping nonvolatile memory cells is arranged in several columns of cells, each arranged in a series, such as a NAND string. Each cell stores no more than a single charge storage...
7394708 Adjustable global tap voltage to improve memory cell yield  
A system that increases device yield by correcting improper operation of the device's memory cells due to process variations is disclosed. The device includes an array of memory cells and an...
7394694 Flash memory device with NAND architecture with reduced capacitive coupling effect  
A NAND flash memory device includes a matrix of memory cells each having a threshold voltage. The matrix includes an individually erasable sector and is arranged in plural rows and columns with the...
7394307 Voltage regulator having reverse voltage protection and reverse current prevention  
A voltage regulator having a MOS transistor driver includes a p-channel MOS transistor at a voltage input terminal Vin and a p-channel MOS transistor at a voltage output terminal Vout. A drain of...
7394686 Programmable structure including discontinuous storage elements and spacer control gates in a trench  
A semiconductor storage cell includes first and second source/drain regions underlying first and second trenches defined in a semiconductor substrate. Sidewalls of the trenches are lined with a...
7394700 Programming methods for a nonvolatile memory device using a Y-scan operation during a verify read operation  
Some embodiments of the present invention provide programming operations for reducing a program time for a nonvolatile memory device. A nonvolatile semiconductor memory device is programmed by...
7391647 Non-volatile memory in CMOS logic process and method of operation thereof  
A non-volatile memory (NVM) cell fabricated on a semiconductor substrate, and including a floating gate electrode (which extends at least partially over all active regions of the NVM cell). The NVM...
7388779 Multiple level programming in a non-volatile device  
The programming method of the present invention minimizes program disturb by initially programming cells on the same wordline with the logical state having the highest threshold voltage. The...
7388787 Reference current generator  
In a reference current generator, a current mirror has a referent branch with a first current flowing thereon and a mirror branch to produce a second current by mirroring the first current, a first...
7388785 Method for extracting the distribution of charge stored in a semiconductor device  
A method is described for extracting the spatial distribution of charge stored in a charge-trapping layer of a semiconductor device. The method comprises the steps of performing a first...
7385847 Semiconductor device  
A semiconductor device includes an electrical circuit formed on a substrate; a level detector outputting a first level signal which has a signal level based on power supply voltage and which...
7385846 Reduction of adjacent floating gate data pattern sensitivity  
The method for programming non-volatile memory cells erases the memory cells to be programmed. The memory cells are then programmed to a reduced floating gate voltage that takes into account...
7385868 Method of refreshing a PCRAM memory device  
A method for refreshing PCRAM cells programmed to a low resistance state and entire arrays of PCRAM cells uses a simple refresh scheme which does not require separate control and application of...
Matches 351 - 400 out of 1794 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >