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7102930 |
Method of programming a non-volatile memory cell to eliminate or to minimize program deceleration
A method to eliminate program deceleration and to enhance the resistance to program disturbance of a non-volatile floating gate memory cell is disclosed. This method eliminates or minimizes the...
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7098505 |
Memory device with multiple memory layers of local charge storage
A multiple memory layer device has a plurality of stacked memory layers. Each of the memory layers has: a charge generating layer of p-type semiconductor material with a plurality of n-type...
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7099220 |
Methods for erasing flash memory
Methods for erasing flash memory using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a second polarity during an erase period.
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7099194 |
Error recovery for nonvolatile memory
An error recovery technique is used on marginal nonvolatile memory cells. A marginal memory cell is unreadable because it has a voltage threshold (VT) of less than zero volts. By biasing adjacent...
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7099193 |
Nonvolatile semiconductor memory device, electronic card and electronic apparatus
A nonvolatile semiconductor memory device includes a NAND cell with a plurality of electrically data rewritable memory cells being connected in series, word lines connected to control gates of the...
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7099195 |
Methods for neutralizing holes in tunnel oxides of floating-gate memory cells and devices
Methods for neutralizing holes in tunnel oxides of floating-gate memory cells and devices using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a...
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7095076 |
Electrically-alterable non-volatile memory cell
A method, apparatus, and system in which an embedded memory comprises one or more electrically-alterable non-volatile memory cells that include a coupling capacitor, a read transistor, and a...
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7095654 |
Method and system for programming and inhibiting multi-level, non-volatile memory cells
A multi-level non-volatile memory cell programming/lockout method and system are provided. The programming/lockout method and system advantageously prevent memory cells that charge faster than...
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7092297 |
Method for pulse erase in dual bit memory devices
The present invention provides a method for erasing floating gate memory devices. Specifically, one embodiment of the present invention discloses a method for erasing an array of non-volatile flash...
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7092291 |
Nonvolatile semiconductor memory device, charge injection method thereof and electronic apparatus
A charge injection method for improving the efficiency of generating hot carriers, wherein, for example, electrons are injected at writing and holes are injected at erasing to a charge storage...
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7092294 |
Nonvolatile semiconductor memory
A semiconductor memory includes a memory cell array having a memory cell units, configured from memory cell transistors connected in a column, which have a first and a second control gate disposed...
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7092290 |
High speed programming system with reduced over programming
A program pulse is applied to a set of non-volatile storage elements. The magnitude of the program pulse is chosen to be low enough such that no non-volatile storage elements will be over...
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7088623 |
Non-volatile memory technology suitable for flash and byte operation application
The present invention provides a non-volatile memory cell structure suitable for the flash memory cell and EEPROM cell (electrically erasable programmable read only memory cell) to perform the byte...
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7088621 |
Bitline governed approach for coarse/fine programming
In a system for programming non-volatile storage, technology is disclosed for programming with greater precision and reasonable program times. In one embodiment, a first voltage is applied to a bit...
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7088615 |
Multi-state memory
Maximized multi-state compaction and more tolerance in memory state behavior is achieved through a flexible, self-consistent and self-adapting mode of detection, covering a wide dynamic range. For...
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7088614 |
Programming method for a multilevel memory cell
A programming method of a multilevel memory cell is able to store a plurality of bits in a plurality of levels. The method includes writing a logic value in the multilevel memory cell by setting...
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7085157 |
Nonvolatile memory device and semiconductor device
A method for speeding up data writing and reducing power consumption by reducing the variation of the threshold voltage of each of non-volatile memory cells at data writing. When writing data in a...
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7085163 |
Gate voltage regulation system for a non-volatile memory cells programming and/or soft programming phase
A plurality of non volatile memory cells, for example of the flash type, with low circuit area occupation, are organized in cell matrices with corresponding circuits responsible for addressing,...
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7085165 |
Method and apparatus for reducing read disturb in non-volatile memory
A memory cell with a charge-trapping structure stores multiple bits. A biasing arrangement is applied to one part of the charge-trapping structure of the memory cell to store a high threshold...
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7085164 |
Programming methods for multi-level flash EEPROMs
A method is provided for programming a memory cell of an electrically erasable programmable read only memory. The memory cell is fabricated on a substrate and comprises a source region, a drain...
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7082060 |
Soft programming for recovery of overerasure
A method of erasing a memory cell includes the step of erasing a memory cell. The current in the memory cell is measured. If the measured memory cell current approximately exceeds a predetermined...
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7082057 |
Semiconductor memory device
A semiconductor memory device includes a field-effect transistor provided on a surface of a P-type transistor substrate. The field-effect transistor includes two N-type diffusion layer regions, a...
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7079437 |
Nonvolatile semiconductor memory device having configuration of NAND strings with dummy memory cells adjacent to select transistors
A nonvolatile semiconductor memory device having a plurality of electrically rewritable nonvolatile memory cells connected in series together is disclosed. A select gate transistor is connected in...
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7075831 |
Method for erasing an NROM cell
An operation to erase a nitride read only memory (NROM) memory block starts by erasing the memory block. An erase verify operation can then be performed to determine the success of the erase. If a...
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7075830 |
Method for programming single-bit storage SONOS type memory
A method for programming a single-bit storage nonvolatile memory cell includes the steps of: providing a single-bit storage nonvolatile memory cell having a channel region between a left bit line...
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7075832 |
Method for erasing an NROM cell
An operation to erase a nitride read only memory (NROM) memory block starts by erasing the memory block. An erase verify operation can then be performed to determine the success of the erase. If a...
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7075827 |
Function reconfigurable semiconductor device and integrated circuit configuring the semiconductor device
A function reconfigurable semiconductor device is provided. The function reconfigurable semiconductor device includes a plurality of function cells, each of the function cells being a basic unit...
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7075824 |
NAND flash memory device
Disclosed is a NAND flash memory device which includes butting taps that are formed in such a manner that a poly layer and a silicide layer are connected to given points at the ends of a DSL and...
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7075828 |
Operation scheme with charge balancing erase for charge trapping non-volatile memory
A method of operating a memory cell comprises applying a first procedure (typically erase) to establish a low threshold state including a first bias arrangement causing reduction in negative charge...
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7072220 |
Method and apparatus for operating a non-volatile memory array
A string of memory cells with a charge trapping structure coupled in series is read, by measuring current that flows between the body region of the selected memory cell and the contact region of...
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7072226 |
Method of erasing a flash memory cell
Methods are disclosed for erasing a flash memory cell including: (a) a semiconductor substrate, (b) a gate, (c) a source, (d) a drain, (e) a well, the gate including: (1) a tunnel oxide film, (2) a...
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7072218 |
Semiconductor integrated circuit, semiconductor non-volatile memory, memory card, and microcomputer
A high voltage output driver derives operational power from high voltages and a switching circuit which reverses the output state of the high voltage output driver. The high voltage output driver...
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7068543 |
Flash memory
Flash memory supporting methods for erasing memory cells using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a second...
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7064983 |
Method for programming a reference cell
A method for programming one or more reference cells is described. The reference cell is programmed a predetermined amount, its program state is sensed relative to a prescribed cell on the same die...
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7064982 |
Semiconductor memory device and portable electronic apparatus
A semiconductor memory device includes a memory cell including a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed under the gate electrode,...
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7064980 |
Non-volatile memory and method with bit line coupled compensation
When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it...
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7064984 |
Circuit and method for reducing leakage current in a row driver circuit in a flash memory during a standby mode of operation
A row driver receives an input signal and a test mode signal, and is coupled to first and second voltage sources and has an output coupled to a word line. The row driver operates in an active mode...
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7064981 |
NAND string wordline delay reduction
An improved NAND Flash memory and word line selection method has been described, that takes advantage of the asymmetric nature of the word line to word line capacitive coupling to reduce word line...
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7061806 |
Floating-body memory cell write
A system to write to a plurality of memory cells coupled to a word line, each of the plurality of memory cells comprising a transistor having a source, a drain, a body and a gate coupled to the...
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7057931 |
Flash memory programming using gate induced junction leakage current
A method for programming a storage element and a storage element programmed using gate induced junction leakage current are provided. The element may include at least a floating gate on a...
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7057945 |
Non-volatile memory erase circuitry
A non-volatile memory device includes floating gate memory cells, a pulse counter and voltage pump control circuitry. The control circuitry selectively activates pumps in response to a count output...
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7054198 |
Flash memory with fast boot block access
A flash memory device and system include a boot block voltage pump for providing a word line voltage to the boot block of the flash memory. At least one additional voltage pump is provided to...
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7054196 |
Method for programming P-channel EEPROM
A method for programming a P-channel EEPROM having an N-well, a floating gate, a control gate, a P-type source region and a P-type drain region is provided. In the method, the N-well is grounded, a...
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7054193 |
Non-uniform programming pulse width for writing of multi-bit-per-cell memories
Write operations that simultaneously program multiple memory cells on the same word line in an MBPC Flash memory employ word line voltage variation, programming pulse width variation, and...
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7053442 |
Nonvolatile semiconductor memory device
A nonvolatile semiconductor memory device having a small layout area includes a memory cell array in which a plurality of memory cells are arranged in a row direction and a column direction. The...
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7054197 |
Method for reading a nonvolatile memory device and nonvolatile memory device implementing the reading method
A reading method for a nonvolatile memory device, wherein the gate terminals of the array memory cell and of the reference memory cell are supplied with a same reading voltage having a ramp-like...
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7050336 |
Nonvolatile semiconductor memory device having reduced erasing time
An operation of erasing data in a memory block of a nonvolatile semiconductor memory device employs an operation of collectively applying an erase pulse to the memory block, and an operation of...
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7046551 |
Nonvolatile memories with asymmetric transistors, nonvolatile memories with high voltage lines extending in the column direction, and nonvolatile memories with decoding circuits sharing a common area
Nonvolatile memory cells ( 110 ) are connected to a bitline (BL 170 ). The bitline is also connected to a source/drain region ( 620 ) of a transistor ( 610 ), a Y multiplexer transistor for...
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7046553 |
Fast program to program verify method
In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of...
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7046554 |
Page buffer of flash memory device and data program method using the same
Disclosed are a page buffer of a flash memory device and data program method using the same. After two data are sequentially stored in a main register (first latch) and a cache register (second...
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