|
Match
|
Document |
Document Title |
|
|
7170796 |
Methods and systems for reducing the threshold voltage distribution following a memory cell erase
A method is provided for erasing a memory device including a number of memory cells, the memory cells including a substrate, a control gate, a charge storage element, a source region and a drain...
|
|
|
7170793 |
Programming inhibit for non-volatile memory
A non-volatile memory system is programmed so as to reduce or avoid program disturb. In accordance with one embodiment, the storage elements of a NAND string are partitioned into at least two...
|
|
|
7170786 |
Deep wordline trench to shield cross coupling between adjacent cells for scaled NAND
A NAND flash memory structure with a wordline or control gate that provides shielding from Yupin effect errors and generally from potentials in adjacent strings undergoing programming operations...
|
|
|
7170788 |
Last-first mode and apparatus for programming of non-volatile memory with reduced program disturb
A non-volatile memory is programmed in a manner which reduces the incidence of program disturb for inhibited memory elements which undergo boosting to reduce program disturb, but which experience...
|
|
|
7167399 |
Flash memory device with a variable erase pulse
A method of operating a flash memory device according to an embodiment of the present invention includes selecting a flash cell in a flash memory device to undergo an erase, applying a long erase...
|
|
|
7164603 |
Operation scheme with high work function gate and charge balancing for charge trapping non-volatile memory
A memory cell with a charge trapping structure has multiple bias arrangements. Multiple cycles of applying the bias arrangements lowering and raising a threshold voltage of the memory cell leave a...
|
|
|
7161834 |
Memory card and data processing system
A memory card and a microcomputer with nonvolatile memory wherein operation under two different types of power supply specifications achieved are provided. A MultiMediacard includes a flash memory...
|
|
|
7161833 |
Self-boosting system for flash memory cells
A low voltage of the order of or one to three volts instead of an intermediate V PASS voltage (e.g. of the order of five to ten volts) is applied to word line zero immediately adjacent to the...
|
|
|
7158411 |
Integrated code and data flash memory
A memory architecture for an integrated circuit comprises a first memory array configured to store data for one pattern of data usage and a second memory array configured to store data for another...
|
|
|
7158413 |
Semiconductor memory device with MOS transistors, each including a floating gate and a control gate, a control method thereof, and a memory card including the same
A semiconductor memory device includes memory cells, write bit lines, read bit lines, latch circuits, a n-channel MOS transistor, and voltage setting circuits. The memory cell includes a first MOS...
|
|
|
7158414 |
Reference sensing circuit
A reference voltage generator circuit for nonvolatile memory devices is disclosed. The circuit has at least one sense amplifier bias reference voltage generator (SABRVG) for generating a reference...
|
|
|
7154786 |
Semiconductor integrated circuit device
A nonvolatile memory working on a different operating voltage from a logical functional unit is to be operated at high speed with a single line voltage supplied from outside. A nonvolatile memory...
|
|
|
7154785 |
Charge pump circuitry having adjustable current outputs
Methods and apparatus are provided. A memory device includes charge pump circuitry having a plurality of parallel charge pumps for supplying a programming voltage to an array of memory cells of the...
|
|
|
7154153 |
Memory device
A floating gate transistor has a reduced barrier energy at an interface with an adjacent gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is stored...
|
|
|
7154794 |
Memory regulator system with test mode
A system for switching between a read mode and a write mode. The system includes a voltage regulating circuit and a memory array. The voltage regulating circuit includes a voltage input and a...
|
|
|
7151702 |
High voltage generators having an integrated discharge path for use in non-volatile semiconductor memory devices
High voltage generators include a charge pump and a ripple reduction circuit that includes an integrated discharge path. The ripple reduction circuit limits the voltage level from a charge pump...
|
|
|
7151682 |
Method and apparatus to read information from a content addressable memory (CAM) cell
A method and apparatus to read information from a content addressable memory (CAM) cell of a nonvolatile memory is provided. The apparatus may be a nonvolatile memory that may include a first...
|
|
|
7151693 |
Method of writing data to a non-volatile semiconductor memory
A method of writing data into a non-volatile semiconductor memory having a plurality of memory cells in which a word line is shared by memory cells and a bit line is shared by adjacent memory...
|
|
|
7149119 |
System and method of controlling a three-dimensional memory
A system and method of controlling a three dimensional memory is disclosed. In a particular embodiment, the system is implemented as an integrated circuit including a microcontroller having a...
|
|
|
7149117 |
Reduction of adjacent floating gate data pattern sensitivity
The method for programming non-volatile memory cells erases the memory cells to be programmed. The memory cells are then programmed to a reduced floating gate voltage that takes into account...
|
|
|
7149118 |
Method and apparatus for programming single-poly pFET-based nonvolatile memory cells
Methods and apparatuses for programming a single-poly pFET-based nonvolatile memory cell bias the cell so that band-to-band tunneling (BTBT) is induced and electrons generated by the BTBT are...
|
|
|
7149124 |
Boosted substrate/tub programming for flash memories
A boosted substrate tub/substrate floating gate memory cell programming process is described that applies a voltage to the substrate or substrate “tub” of a NAND Flash memory array to precharge...
|
|
|
7149109 |
Single transistor vertical memory gain cell
A high density vertical single transistor gain cell is realized for DRAM operation. The gain cell includes a vertical transistor having a source region, a drain region, and a floating body region...
|
|
|
7145802 |
Programming and manufacturing method for split gate memory cell
A method for programming a split gate memory cell comprises the following steps. First, a split gate memory cell formed on a semiconductor substrate of a first conductive type, e.g., p-type, is...
|
|
|
7145808 |
Nonvolatile semiconductor memory apparatus and method of producing the same
A nonvolatile semiconductor memory apparatus suitable to logic incorporation, by which a charge injection efficiency is high and hot electrons (HE) can be effectively injected at a low voltage is...
|
|
|
7145794 |
Programmable microelectronic devices and methods of forming and programming same
A microelectronic programmable structure and methods of forming and programming the structure. The programmable structure generally include an ion conductor and a plurality of electrodes....
|
|
|
7142454 |
System and method for Y-decoding in a flash memory device
A system and method for column selection in a non-volatile memory cell array is disclosed. A group of memory cells is arranged in a rectangular array having rows (X-dimension) and columns...
|
|
|
7139188 |
Memory architecture and method of manufacture and operation thereof
An architecture, and its method of formation and operation, containing a high density memory array of semi-volatile or non-volatile memory elements, including, but not limited to, programmable...
|
|
|
7139202 |
Semiconductor storage device, mobile electronic apparatus, and method for controlling the semiconductor storage device
A semiconductor storage device is provided, which comprises a memory array comprising memory elements, a write state machine for applying a first voltage for performing a write or erase operation,...
|
|
|
7139197 |
Voltage regulation system for a multiword programming of a low integration area non volatile memory
The invention relates to a voltage regulation system for multiword programming in non volatile memories, for example of the Flash type, with low circuit area occupation, wherein memories comprise...
|
|
|
7136307 |
Write state machine architecture for flash memory internal instructions
A system and method for a write state machine for non-volatile memory is disclosed. The write state machine has an associated read only memory for storing instructions for operation of the...
|
|
|
7133317 |
Method and apparatus for programming nonvolatile memory
Programming nonvolatile memory cells is affected by the program disturb effect which causes data accuracy issues with nonvolatile memory. Rather than masking the voltage conditions that cause the...
|
|
|
7133313 |
Operation scheme with charge balancing for charge trapping non-volatile memory
A memory cell with a charge trapping structure has multiple bias arrangements. Multiple cycles of applying the bias arrangements lowering and raising a threshold voltage of the memory cell leave a...
|
|
|
7133316 |
Program/erase method for P-channel charge trapping memory device
A method of operating a memory device is disclosed, wherein the memory device includes an n-type substrate and a plurality of memory cells formed thereon, each memory cell corresponding to a word...
|
|
|
7130220 |
Write once read only memory employing floating gates
Structures and methods for write once read only memory employing floating gates are provided. The write once read only memory cell includes a floating gate transistor formed in a modified dynamic...
|
|
|
7130219 |
Electrically word-erasable non-volatile memory device, and biasing method thereof
A memory device formed by an array of memory cells extending in rows and columns. The device is formed by a plurality of N-type wells extending parallel to the rows; each N-type well houses a...
|
|
|
7130215 |
Method and apparatus for operating a non-volatile memory device
A nonvolatile memory cell with a charge trapping structure coupled in series is read, by measuring current that flows between the body region of the nonvolatile memory cell and the contact region...
|
|
|
7130221 |
Dual gate multi-bit semiconductor memory
A method for altering and reading the contents of a memory cell includes the steps of: applying programming voltages to a first control gate and to a second control gate to cause carriers to be...
|
|
|
7130222 |
Nonvolatile memory with program while program verify
A page mode program sequence is described that includes first and second bias applying cycles. In the first cycle, a program bias is applied to a first part of a page of memory cells, while a...
|
|
|
7130218 |
Nonvolatile memory with controlled voltage boosting speed
In a nonvolatile memory in which a load on a boosting circuit changes according to the number of rewrite bytes, the boosting circuit is configured so as to perform voltage boosting at a relatively...
|
|
|
7126854 |
Technique for programming floating-gate transistor used in circuitry as flash EPROM
The sequence in which the voltages (V SL , V DL , V SG , and V CL ) applied to the source/drain regions (S and D), select gate (SG), and (if present) control gate (CG) of a floating-gate...
|
|
|
7126872 |
Semiconductor integrated circuit
In view of controlling overshoot when the power supply is inputted without increase in the area occupied with a chip in a voltage generating circuit mounted over a semiconductor integrated circuit,...
|
|
|
7123503 |
Writing to ferroelectric memory devices
A programming voltage is applied to a first word line coupled to a control gate of a selected ferroelectric memory cell in an array of ferroelectric memory cells. A gate/source voltage equal to the...
|
|
|
7120057 |
Semiconductor memory device with a stacked gate including a floating gate and a control gate
A semiconductor memory device comprises a first to a fourth semiconductor layer of a first conductivity type which are formed in a fifth semiconductor layer of a second conductivity type in such a...
|
|
|
7120061 |
Method and apparatus for a dual power supply to embedded non-volatile memory
A charge pump is configured to receive an external voltage level and generate a high voltage level, wherein the high voltage level is higher than the external voltage level. A memory control...
|
|
|
7120058 |
Circuit and method for controlling boosting voltage
A circuit for use in a memory device is provided, comprising: a level detector that receives a plurality of programming input signals, detects which of the programming input signals are active, and...
|
|
|
7115942 |
Method and apparatus for nonvolatile memory
Method and apparatus on charges injection using piezo-ballistic-charges injection mechanism are provided for nonvolatile memory device. The device has a strain source, an injection filter, a...
|
|
|
7116579 |
Semiconductor storage device and mobile electronic apparatus
A semiconductor storage device is provided, which comprises a memory array comprising memory elements, a write state machine for performing a sequence of a program or erase operation with respect...
|
|
|
7113430 |
Device for reducing sub-threshold leakage current within a high voltage driver
A device for reducing the effects of leakage current within electronic devices is disclosed. In one form, a high voltage driver includes a high voltage source coupled to at least one high voltage...
|
|
|
7113428 |
Method for operating a memory cell array
Prior to the reprogramming of a selected flash memory cell of a memory cell array, electrons being removed from the memory layer (M) in the channel region (C) by Fowler-Nordheim tunneling, a lower...
|