|
Match
|
Document |
Document Title |
|
|
7224614 |
Methods for improved program-verify operations in non-volatile memories
In programming a non-volatile memory involving alternately applying a programming pulse and verifying the programming, time is saved in the program verify portion when, depending on the states of...
|
|
|
7224610 |
Layout reduction by sharing a column latch per two bit lines
Increasing levels of integration in successive generations of semiconductor memory products are possible through minimal metal-one layout pitches. An optimal bitline layout pitch in metal-one...
|
|
|
7221592 |
Multiple level programming in a non-volatile memory device
The programming method of the present invention minimizes program disturb by initially programming cells on the same wordline with the logical state having the highest threshold voltage. The...
|
|
|
7221590 |
Flash memory devices having power level detection circuits
Flash memory devices are provided including a power supply pad unit. The power supply pad unit includes a first power supply pad, a second power supply pad and a power level detection circuit. The...
|
|
|
7221596 |
pFET nonvolatile memory
A nonvolatile memory cell is constructed using a floating-gate (FG) pFET Readout Transistor (RT) having its source tied to a power source (Vdd) and its drain providing a current which can be sensed...
|
|
|
7221587 |
Semiconductor device and programming method
The semiconductor device of the present invention includes a column decoder (select and write circuit), which selects multiple pages that are not located adjacently to each other so as to...
|
|
|
7218552 |
Last-first mode and method for programming of non-volatile memory with reduced program disturb
A non-volatile memory is programmed in a manner which reduces the incidence of program disturb for inhibited memory elements which undergo boosting to reduce program disturb, but which experience...
|
|
|
7215576 |
Nonvolatile semiconductor memory device which erases data in units of one block including a number of memory cells, and data erasing method of the nonvolatile semiconductor memory device
In a data erasing method of a nonvolatile semiconductor memory device, cells are subjected to the processings of executing programming by applying a voltage to the cells to set their threshold...
|
|
|
7215578 |
Method and apparatus for driving flash memory
A method for driving a flash memory and flash memory apparatus thereof are provided. The flash memory apparatus comprises a flash memory controller and a flash memory. At first, a voltage level of...
|
|
|
7212442 |
Structure for directly burning program into motherboard
The present invention relates to a structure for directly burning a program into a motherboard comprising a burning plate having a series connected first transistor set, a resistor, a comparator...
|
|
|
7212443 |
Non-volatile memory and write method of the same
A non-volatile memory in which a plurality of memory cells connected to a same word line are entirely written with data. Source lines SL separated from each other in column units is arranged on...
|
|
|
7212437 |
Charge coupled EEPROM device and corresponding method of operation
This invention provides a semiconductor memory device and a corresponding method of operation. The semiconductor memory device comprises a semiconductor substrate having a first conductivity; a...
|
|
|
7209794 |
Controller with interface attachment
A controller with attachments for controlling specific electronic circuits is disclosed. Each attachment has a connector connectable to the electronic circuit to be controlled, and a memory...
|
|
|
7206235 |
Apparatus for controlled programming of non-volatile memory exhibiting bit line coupling
The effects of bit line-to-bit line coupling in a non-volatile memory are addressed. An inhibit voltage is applied on a bit line of a storage element to be programmed to inhibit programming during...
|
|
|
7206228 |
Block switch in flash memory device
Disclosed herein is a block switch of a flash memory device in which a voltage higher than a predetermined operating voltage is generated to drive path transistors in order to stably apply the...
|
|
|
7206241 |
Semiconductor device and programming method
The semiconductor device of the present invention includes at least one dummy cell of a programmed state proximately located to an edge of a reference cell array. Thus, the leak current does not...
|
|
|
7203087 |
Fast reading, low consumption memory device and reading method thereof
A memory device having a reading configuration and including a plurality of memory cells, arranged in rows and columns, memory cells arranged on the same column having respective first terminals...
|
|
|
7203118 |
Semiconductor storage device and mobile electronic device
When an input voltage determining circuit 24 determines that an input voltage exceeds a prescribed voltage, a control circuit 25 of a positive polarity power selector circuit 22 turns on a...
|
|
|
7203093 |
Method and apparatus for reading NAND flash memory array
The method for reading/verifying a NAND flash memory device alternates the select gate biasing in response to the position of the cell to be read. If the cell is closer to the top of the column,...
|
|
|
7203095 |
Method for determining programming voltage of nonvolatile memory
A method for determining programming voltage of a nonvolatile memory in which any variation in the threshold voltage at the memory cell after programming by hot carrier injection can be suppressed...
|
|
|
7200040 |
Method of operating p-channel memory
A method of operating a P-channel memory is described. The P-channel memory includes a substrate, a gate formed over the substrate, a charge trapping structure disposed between the substrate and...
|
|
|
7200039 |
Flash memory device with improved erase function and method for controlling erase operation of the same
The present patent relates to flash memory devices with improved erase function, and method of controlling an erase operation of the same. According to the present patent, the flash memory device...
|
|
|
7200058 |
Semiconductor memory device
A semiconductor memory device includes a memory cell array, in which a plurality of electrically rewritable and non-volatile memory cells connected in series and first and second select transistors...
|
|
|
7200045 |
Method for programming a charge-trapping nonvolatile memory cell by raised-Vs channel initialed secondary electron injection (CHISEL)
A raised-Vs Channel Initialed Secondary Electron Injection is disclosed to program a charge-trapping nonvolatile memory cell. The source of the charge-trapping nonvolatile memory cell is applied...
|
|
|
7196930 |
Flash memory programming to reduce program disturb
The method for reducing program disturb in a flash memory array biases a selected wordline at a programming voltage. One of the unselected wordlines, closer to array ground than the selected...
|
|
|
7196938 |
Charge-sharing technique during flash memory programming
A non-volatile memory cell array, such as a Flash NOR array, is programmed by applying voltages to bit lines that connect to memory cells in the memory cell array. A first bit line corresponding to...
|
|
|
7196943 |
Memory device
A semiconductor memory device includes a plurality of memory cells arranged according to a plurality of rows and a plurality of columns. The memory devices further includes a plurality of bit...
|
|
|
7193902 |
Method of erasing a flash memory cell
Methods are disclosed for erasing a flash memory cell including: (a) a semiconductor substrate, (b) a gate, (c) a source, (d) a drain, (e) a well, the gate including: (1) a tunnel oxide film, (2) a...
|
|
|
7187595 |
Replenishment for internal voltage
A replenish circuit for a semiconductor memory device, including a bias current generating unit adapted to generate a bias current, a frequency controllable oscillator adapted to receive the bias...
|
|
|
7187589 |
Non-volatile semiconductor memory and method for writing data into a non-volatile semiconductor memory
Data is written into a non-volatile semiconductor memory using one of at least four steps. A first step is executed if the final states of both the first bit (B 1 ) and the second bit (B 2 )...
|
|
|
7187588 |
Semiconductor storage
A semiconductor storage device includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a single gate electrode formed on the gate insulating film, two...
|
|
|
7184308 |
Flash memory devices and methods for programming the same
A flash memory device having a memory cell string is programmed. The flash memory device includes a plurality of memory cells. During a programming cycle, application of a program voltage to a...
|
|
|
7184317 |
Method for programming multi-bit charge-trapping memory cell arrays
A programming voltage is applied to source and drain in order to generate hot-hole injection at one end of the channel of a memory cell. The undesired programming of a neighboring memory cell is...
|
|
|
7184316 |
Non-volatile memory cell array having common drain lines and method of operating the same
A nonvolatile memory cell array having common drain lines and method of operating the same are disclosed. A positive voltage is applied to a gate of a selected cell and gates of memory cells that...
|
|
|
7184309 |
Non-volatile semiconductor memory device
A non-volatile semiconductor memory device having a write mode in which wrong writing is prevented surely. The storage device comprises a NAND cell comprising a plurality of memory transistors...
|
|
|
7180790 |
Non-volatile memory device having controlled bulk voltage and method of programming same
Disclosed is a non-volatile memory device and a method of programming the same. The non-volatile memory device is programmed by applying a wordline voltage, a bitline voltage, and a bulk voltage to...
|
|
|
7180785 |
Nonvolatile semiconductor memory device with a plurality of sectors
A nonvolatile semiconductor memory device is disclosed that comprises plural sectors each including a memory cell array, plural word line drivers provided in each one of the sectors to drive...
|
|
|
7180779 |
Memory architecture with enhanced over-erase tolerant control gate scheme
The present invention is related to semiconductor memories, and in particular, to a nonvolatile or flash memory and method that reduces the effect of or is tolerant of over-erased memory cells....
|
|
|
7177193 |
Programmable fuse and antifuse and method therefor
P-channel MOSFET devices are used as reprogrammable fuse or antifuse elements in a memory decode circuit by utilizing anomalous hole generation. An applied negative gate bias voltage is...
|
|
|
7177195 |
Reducing the effects of noise in non-volatile memories through multiple reads
Storage elements are read multiple times and the results are accumulated and averaged for each storage element to reduce the effects of noise or other transients in the storage elements and...
|
|
|
7177197 |
Latched programming of memory and method
Operating voltages to a group of memory cells in an array are supplied via access lines such as word lines and bit lines. The capacitance of associated nodes of the memory cells can latch some of...
|
|
|
7173861 |
Nonvolatile memory device for preventing bitline high voltage from discharge
According to some embodiments, a nonvolatile semiconductor memory device includes high voltage circuits that prevent high voltages, which are applied to bitlines during an erase operation, from...
|
|
|
7173849 |
Method of programming and erasing multi-level flash memory
A programming method of the multi-level flash memory comprises shooting a programming voltage that is increasing upwards stepwise each time into the gate of the multi-level flash memory, and...
|
|
|
7170795 |
Electrically erasable charge trap nonvolatile memory cells having erase threshold voltage that is higher than an initial threshold voltage
An electrically erasable charge trap nonvolatile memory cell has an initial threshold voltage, a program voltage that is higher than the initial threshold voltage, and an erase threshold voltage...
|
|
|
7170796 |
Methods and systems for reducing the threshold voltage distribution following a memory cell erase
A method is provided for erasing a memory device including a number of memory cells, the memory cells including a substrate, a control gate, a charge storage element, a source region and a drain...
|
|
|
7170793 |
Programming inhibit for non-volatile memory
A non-volatile memory system is programmed so as to reduce or avoid program disturb. In accordance with one embodiment, the storage elements of a NAND string are partitioned into at least two...
|
|
|
7170786 |
Deep wordline trench to shield cross coupling between adjacent cells for scaled NAND
A NAND flash memory structure with a wordline or control gate that provides shielding from Yupin effect errors and generally from potentials in adjacent strings undergoing programming operations...
|
|
|
7170788 |
Last-first mode and apparatus for programming of non-volatile memory with reduced program disturb
A non-volatile memory is programmed in a manner which reduces the incidence of program disturb for inhibited memory elements which undergo boosting to reduce program disturb, but which experience...
|
|
|
7167399 |
Flash memory device with a variable erase pulse
A method of operating a flash memory device according to an embodiment of the present invention includes selecting a flash cell in a flash memory device to undergo an erase, applying a long erase...
|
|
|
7164603 |
Operation scheme with high work function gate and charge balancing for charge trapping non-volatile memory
A memory cell with a charge trapping structure has multiple bias arrangements. Multiple cycles of applying the bias arrangements lowering and raising a threshold voltage of the memory cell leave a...
|