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7372734 Methods of operating electrically alterable non-volatile memory cell  
A nonvolatile memory cell is provided. The memory cell includes a storage transistor and an injector in a well of an n-type conductivity. The well is formed in a semiconductor substrate of a p-type...
7372732 Pulse width converged method to control voltage threshold (Vt) distribution of a memory cell  
A method of operating on a plurality of non-volatile multi-level memory cells is disclosed. The memory cells have at least a first, second, third and fourth program level. Each of program levels...
7345916 Method and apparatus for high voltage operation for a high performance semiconductor memory device  
A method and apparatus are provided for high performance, high voltage memory operations on selected memory cells ( 200 ) of a semiconductor memory device ( 100 ). A high voltage generator ( 106 )...
7345915 Modified-layer EPROM cell  
An EPROM cell includes a semiconductor substrate, having source and drain regions, a floating gate, including a semiconductive polysilicon layer electrically interconnected with a first metal...
7339834 Starting program voltage shift with cycling of non-volatile memory  
A system is disclosed for programming non-volatile storage that improves performance by setting the starting programming voltage to a first level for fresh parts and adjusting the starting...
7339827 Non-volatile semiconductor memory device and writing method thereof  
In connection with rise and fall of a word line bias, the present invention adopts a procedure such that a diffusion region voltage Vs on a memory transistor side is changed, and after the voltage...
7339826 Threshold voltage shift in NROM cells  
An NROM (nitride read only memory) cell, which is programmed by channel hot electron injection and erased by hot hole injection, includes a charge trapping structure formed of: a bottom oxide...
7336539 Method of operating flash memory cell  
A flash memory cell is provided. A deep well is disposed in a substrate and a well is disposed within the deep well. A stacked gate structure is disposed on the substrate. A source region and a...
7336530 CMOS pixel with dual gate PMOS  
A pixel circuit with a dual gate PMOS is formed by forming two P + regions in an N − well. The N − well is in a P − type substrate. The two P + regions form the source and drain of a...
7321511 Semiconductor device and method for controlling operation thereof  
A semiconductor device includes a semiconductor substrate, word lines, global bit lines, and inversion gates that form inversion layers serving as local bit lines in the semiconductor substrate....
7319615 Ramp gate erase for dual bit flash memory  
A method of erasing a block of flash memory cells by applying a ramped gate erase voltage to the block of memory cells. When an erase verify of the block of memory cells indicates that erasure has...
7317634 Nonvolatile semiconductor memory device  
The programming speed of a nonvolatile semiconductor memory device used as a flash memory is increased as follows. First, second, and third assist gates, a control gate, as well as first and second...
7307882 Non-volatile memory  
A non-volatile memory having a gate structure, a pair of storage units and two assist gates is provided. The gate structure is disposed on the substrate. The storage units are disposed on the...
7307880 One time programming memory cell using MOS device  
An electroless plating apparatus is provided. The electroless plating apparatus includes a wafer holder; a chemical dispensing nozzle over the wafer holder; a conduit connected to the chemical...
7295473 System for reducing read disturb for non-volatile storage  
A system for reducing or removing a form of read disturb in a non-volatile storage device. One embodiment seeks to prevent read disturb by eliminating or minimizing boosting of the channel of the...
7292475 Nonvolatile memory device and data write method for nonvolatile memory device  
A nonvolatile memory device, including a plurality of memory cell blocks, N memory cell blocks (N is an integer equal to or greater than 2) being arranged in a row direction, L memory cell blocks...
7289365 Nonvolatile semiconductor memory device in which write and erase threshold voltages are set at levels symmetrical about neutral threshold voltage of cell transistor  
A semiconductor device includes a memory cell and driver. The memory cell has a cell transistor which has one end of a current path connected to a bit line and stores data by storing charges in a...
7289358 MTP NVM elements by-passed for programming  
Non-Volatile Memory (NVM) cells include a selection circuit for providing an output based on selecting between an input data signal and an output of a Multiple Time Programmable (MTP) NVM element....
7286402 Semiconductor memory device using only single-channel transistor to apply voltage to selected word line  
A semiconductor memory device has a memory cell array, a first transistor of a first conductivity type, a second transistor of a second conductivity type and a third transistor of the first...
7280400 Reducing sneak currents in virtual ground memory arrays  
In a virtual ground memory array, sneak currents between input/output groups of sensed cells may be reduced by providing at least one column of programmed cells between the input/output groups. The...
7263001 Compact non-volatile memory cell and array system  
NVM arrays include rows and columns of NVM cells comprising a floating gate, a programming element, and a logic storage element. During a programming or erase mode, the floating gate of each cell...
7259999 Non-volatile memory cell array for improved data retention and method of operating thereof  
A method is provided which includes erasing a first plurality of non-volatile memory bit cells in a memory block comprising a third plurality of memory bit cells during an erase procedure, such...
7259987 Systems for variable programming of non-volatile memory  
Systems and methods in accordance with various embodiments can provide for reduced program disturb in non-volatile semiconductor memory. In one embodiment, select memory cells such as those...
7239558 Method of hot electron injection programming of a non-volatile memory (NVM) cell array in a single cycle  
A non-volatile memory (NVM) cell splits its basic functions, i.e. program, erase, read and control, among a four PMOS transistor structure, allowing independent optimization of each cell function....
7239555 Erasing method for non-volatile memory  
An erasing method for a non-volatile memory is provided. The method includes the following two major steps. (a) A first voltage is applied to the odd-numbered select gates of each memory row and a...
7236398 Structure of a split-gate memory cell  
A split-gate memory cell includes a memory transistor and a select transistor. The memory transistor includes a drain, a source, a control gate and a floating gate. The select transistor includes a...
7236394 Transistor-free random access memory  
A memory core includes a bit line and a word line. The memory core also includes a core cell in electrical communication with the word line and the bit line. The core cell includes a threshold...
7227780 Semiconductor device and control method thereof  
A semiconductor device including a program voltage supply circuit that supplies a drain of a memory cell with a program voltage, a detection circuit that refers to an output voltage of the program...
7221596 pFET nonvolatile memory  
A nonvolatile memory cell is constructed using a floating-gate (FG) pFET Readout Transistor (RT) having its source tied to a power source (Vdd) and its drain providing a current which can be sensed...
7218552 Last-first mode and method for programming of non-volatile memory with reduced program disturb  
A non-volatile memory is programmed in a manner which reduces the incidence of program disturb for inhibited memory elements which undergo boosting to reduce program disturb, but which experience...
7215571 Method for reducing drain disturb in programming  
For a multi-sectored flash memory array with bitlines spanning multiple erase blocks, a bias scheme for programming an address in any erase sector while minimizing drain voltage induced disturb to...
7212437 Charge coupled EEPROM device and corresponding method of operation  
This invention provides a semiconductor memory device and a corresponding method of operation. The semiconductor memory device comprises a semiconductor substrate having a first conductivity; a...
7203100 Efficient implementation of a read scheme for multi-threaded register file  
A multi-threaded memory system including a plurality of entries, each one of the plurality of entries including a plurality of threads, each one of the plurality of threads including an active cell...
7199424 Scalable flash EEPROM memory cell with notched floating gate and graded source region  
An memory device, and method of making same, that includes source and drain regions defining a channel region therebetween. A select gate is formed over and insulated from a first portion of the...
7199422 Contactless uniform-tunneling separate P-well (CUSP) non-volatile memory array architecture, fabrication and operation  
Floating-gate field-effect transistors or memory cells formed in isolated wells are useful in the fabrication of non-volatile memory arrays and devices. A column of such floating-gate memory cells...
7196930 Flash memory programming to reduce program disturb  
The method for reducing program disturb in a flash memory array biases a selected wordline at a programming voltage. One of the unselected wordlines, closer to array ground than the selected...
7196929 Method for operating a memory device having an amorphous silicon carbide gate insulator  
A floating gate transistor has a reduced barrier energy at an interface with an adjacent amorphous silicon carbide (a-SiC) gate insulator, allowing faster charge transfer across the gate insulator...
7190623 Non-volatile memory cell and method of operating the same  
A memory cell includes an N-type well, three P-type doped regions formed on the N-type well, a dielectric layer formed on the N-type well and between a first doped region and a second doped region...
7187588 Semiconductor storage  
A semiconductor storage device includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a single gate electrode formed on the gate insulating film, two...
7184318 Semiconductor memory device  
Suppressing a leakage current is required in a flash memory because the channel length is made shorter with a reduction in the memory cell size. In an AND type memory array having an assist...
7180774 Semiconductor integrated circuit device including first, second and third gates  
A semiconductor integrated device having a plurality of memory cells, each including a floating gate, a control gate and an auxiliary gate formed over a side surface of the floating gate through an...
7173851 3.5 transistor non-volatile memory cell using gate breakdown phenomena  
A programmable memory cell formed useful in a memory array having column bitlines and row wordlines. The memory cell including a breakdown transistor having its gate connected to a program wordline...
7170788 Last-first mode and apparatus for programming of non-volatile memory with reduced program disturb  
A non-volatile memory is programmed in a manner which reduces the incidence of program disturb for inhibited memory elements which undergo boosting to reduce program disturb, but which experience...
7169671 Method of recording information in nonvolatile semiconductor memory  
A nonvolatile semiconductor memory includes a transistor, one or two resistance-change portions, and one or two charge accumulation portions. The transistor has a control electrode, first main...
7164606 Reverse fowler-nordheim tunneling programming for non-volatile memory cell  
In accordance with a method of programming an NVM array that includes 4-transistor PMOS non-volatile memory (NVM) cells having commonly connected floating gates, for all the cell's in the array...
7161838 Thin film transistor memory device  
A memory device includes a memory array of thin film transistor (TFT) memory cells. The memory cells include a floating gate separated from a gate electrode portion of a gate line by an insulator....
7158428 Semiconductor memory device having hierarchical bit line structure  
A semiconductor memory device comprising: a memory array including a plurality of memory cells; a plurality of word lines corresponding to the respective memory cells; a pair of local bit lines...
7149118 Method and apparatus for programming single-poly pFET-based nonvolatile memory cells  
Methods and apparatuses for programming a single-poly pFET-based nonvolatile memory cell bias the cell so that band-to-band tunneling (BTBT) is induced and electrons generated by the BTBT are...
7149116 Nonvolatile semiconductor memory and programming method for the same  
A semiconductor memory has a memory cell matrix including a plurality of first and second cell columns alternately arranged along a row-direction, each of cell columns is implemented by a plurality...
7136308 Efficient method of data transfer between register files and memories  
A memory system includes an active storage circuit and at least one base storage circuit. The at least one base storage circuit is coupled to the active storage circuit though at least one pass...
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