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7379375 Memory circuits having different word line driving circuit configurations along a common global word line and methods for designing such circuits  
Memory circuits having different configurations of local word line driving circuits (LWLDC) and methods for designing such circuits are provided. The memory circuits include an array of memory...
7379345 Nonvolatile semiconductor memory device that achieves speedup in read operation  
A plurality of first sub-bit lines are each connected to a common source line via a corresponding first sub-bit line reset transistor with NMOS structure, and a plurality of second sub-bit lines...
7366025 Reduced power programming of non-volatile cells  
Methods for minimizing current consumption in a memory array during programming of non-volatile memory cells, such as NROM cells, in the array include: programming a cell without having a direct...
7359240 Flash memory device with multi level cell and burst access method therein  
A flash memory device including memory cells, each memory cell configured to store bits, a sensing circuit configured to sequentially sense, for each memory cell, sets of the bits of the memory...
7355891 Fabricating bi-directional nonvolatile memory cells  
A memory transistor having a pair of separate floating gates overlying end regions of a channel and a control gate that overlies the floating gates and a central region of the channel effectively...
7339825 Nonvolatile semiconductor memory with write global bit lines and read global bit lines  
A nonvolatile semiconductor memory is capable of dual and triple operation with a small chip size. A plurality of sectors is formed. Each sector has nonvolatile memory cells, local bit lines...
7327598 High performance, low leakage SRAM device and a method of placing a portion of memory cells of an SRAM device in an active mode  
An SRAM device and a method of placing a portion of memory cells of an SRAM device in an active mode is provided. In one embodiment, the SRAM device includes a hierarchical grouping of memory cells...
7324402 Flash memory structure  
A flash memory includes: a plurality of switches; a global bit line; and a plurality of memory blocks, each containing a plurality of local bit lines, and a plurality of memory units coupled to the...
7321511 Semiconductor device and method for controlling operation thereof  
A semiconductor device includes a semiconductor substrate, word lines, global bit lines, and inversion gates that form inversion layers serving as local bit lines in the semiconductor substrate....
7317631 Method for reading Uniform Channel Program (UCP) flash memory cells  
A flash memory cell can be read by selecting a local bit line. A read potential is applied to a memory cell transistor associated with the local bit line thereby generating a capacitive loading of...
7315472 Non-volatile memory device  
A non-volatile memory device may include a plurality of memory blocks including memory cells connected in series to bit lines, respectively. Each of the plurality of memory blocks may include a...
7313023 Partition of non-volatile memory array to reduce bit line capacitance  
The present invention that partitions a memory array in N segments by switchably partitioning the bit lines in the array. In the exemplary embodiment, a top set of sense amps control the even bit...
7312503 Semiconductor memory device including MOS transistors each having a floating gate and a control gate  
A semiconductor memory device includes a plurality of memory cells, a plurality of local bit lines, a global bit line, a first switch element, and a holding circuit. The memory cell includes first...
7307885 Multi-value nonvolatile semiconductor memory device equipped with reference cell and load balancing circuit  
A nonvolatile semiconductor memory device includes a plurality of memory cells holding memory cell information, a plurality of bit lines connected to the plurality of memory cells, the plurality of...
7298646 Apparatus for configuring programmable logic devices and associated methods  
A programmable logic device (PLD) includes a non-volatile configuration memory. The non-volatile configuration memory is adapted to configure programmable resources (such as programmable logic and...
7292475 Nonvolatile memory device and data write method for nonvolatile memory device  
A nonvolatile memory device, including a plurality of memory cell blocks, N memory cell blocks (N is an integer equal to or greater than 2) being arranged in a row direction, L memory cell blocks...
7289369 DRAM hierarchical data path  
A hierarchical DRAM array, DRAM macro and logic chip including the DRAM macro embedded in the logic. DRAM array columns are segmented with a small number (e.g., 2-64) of cells connected to a local...
7280425 Dual gate oxide one time programmable (OTP) antifuse cell  
A one-time programmable (OTP) cell includes an access transistor coupled to an antifuse transistor. Access transistor has a gate oxide thickness that is greater than the gate oxide thickness of the...
7259989 Non-volatile memory device  
A non-volatile memory device is disclosed that can reduce the time required for the initialization process. A non-volatile memory device includes a non-volatile memory array having a plurality of...
7245530 Semiconductor memory device with MOS transistors, each including floating gate and control gate, and memory card including the same  
A semiconductor memory device includes memory cells, a memory cell array, bit lines, source lines, word lines, and select gate lines. Each of the memory cells includes a first MOS transistor having...
7233514 Non-volatile semiconductor memory and method for reading a memory cell  
A method for reading a memory cell, wherein the memory cell comprises two source/drain regions and a gate, wherein the source/drain regions are each connected to a respective local bitline, and,...
7233513 Semiconductor memory device with MOS transistors each having floating gate and control gate  
A semiconductor memory device includes memory cells, a memory cell array, word lines, a row decoder, first metal wiring layers, and metal wiring lines. The memory cell includes a first MOS...
7221588 Memory array incorporating memory cells arranged in NAND strings  
An exemplary NAND string memory array includes at least one plane of memory cells, said memory cells comprising thin film modifiable conductance switch devices and which cells are arranged in a...
7209387 Non-volatile programmable fuse apparatus in a flash memory with pairs of supercells programmed in a complementary fashion  
The non-volatile, programmable fuse apparatus has a pair of p-channel transistors coupled in a latch configuration. A supercell is coupled between each transistor and ground. Each supercell is...
7206228 Block switch in flash memory device  
Disclosed herein is a block switch of a flash memory device in which a voltage higher than a predetermined operating voltage is generated to drive path transistors in order to stably apply the...
7200039 Flash memory device with improved erase function and method for controlling erase operation of the same  
The present patent relates to flash memory devices with improved erase function, and method of controlling an erase operation of the same. According to the present patent, the flash memory device...
7193878 Semiconductor memory device layout including increased length connection lines  
An integrated circuit memory device includes a memory cell array including first and second bit lines that extend side-by-side, a plurality of page buffers, a first isolation device electrically...
7190603 Nonvolatile memory array organization and usage  
A non-volatile semiconductor storage device array organization for wide program operations is achieved. The device includes a memory cell array region in which a plurality of C columns and R rows...
7184317 Method for programming multi-bit charge-trapping memory cell arrays  
A programming voltage is applied to source and drain in order to generate hot-hole injection at one end of the channel of a memory cell. The undesired programming of a neighboring memory cell is...
7184307 Flash memory device capable of preventing program disturbance according to partial programming  
A non-volatile semiconductor memory device disclosed herein includes arrays of memory cells arranged along rows and columns. The columns are divided into at least two column regions and each row is...
7180793 Semiconductor non-volatile storage device  
A semiconductor non-volatile storage device of the present invention which lets a memory cell directly drive up to a local bit line, wherein the output of the local bit line is received by a gate...
7180788 Nonvolatile semiconductor memory device  
A non-volatile semiconductor memory device provides for higher integration by reducing the area of occupation of direct peripheral circuits, in which the memory cell of an AND type flash memory...
7180785 Nonvolatile semiconductor memory device with a plurality of sectors  
A nonvolatile semiconductor memory device is disclosed that comprises plural sectors each including a memory cell array, plural word line drivers provided in each one of the sectors to drive...
7170783 Layout for NAND flash memory array having reduced word line impedance  
A memory array including a first region in which a first memory sub-array is located and a second region separated from the first region in which a second memory sub-array is located. The first and...
7164602 Nonvolatile semiconductor memory device including high efficiency and low cost redundant structure  
The PROM area is adjacent to the normal memory cell area. The data writing (normal writing) and the data reading (normal reading) for normal memory cell areas and the data writing (redundant...
7158413 Semiconductor memory device with MOS transistors, each including a floating gate and a control gate, a control method thereof, and a memory card including the same  
A semiconductor memory device includes memory cells, write bit lines, read bit lines, latch circuits, a n-channel MOS transistor, and voltage setting circuits. The memory cell includes a first MOS...
7142460 Flash memory device with improved pre-program function and method for controlling pre-program operation therein  
A flash memory device has an improved pre-program function. The flash memory device comprises memory cell blocks each including wordlines, bitlines, and memory cells sharing common source lines; an...
7133324 Synchronous dynamic random access memory devices having dual data rate 1 (DDR1) and DDR2 modes of operation and methods of operating same  
A dual data rate dynamic random access memory (DDR DRAM) device may operate in dual DDR modes via a mode selection circuit configured to enable a Dual Data Rate (DDR) 1 mode of operation for the...
7133314 Non-volatile semiconductor memory device with reduced chip real estate area for transfer transistors  
A semiconductor memory device that includes a memory cell array with memory cells arranged in rows and columns. The memory cells can also be formed in blocks. A plurality of word lines are applied...
7130219 Electrically word-erasable non-volatile memory device, and biasing method thereof  
A memory device formed by an array of memory cells extending in rows and columns. The device is formed by a plurality of N-type wells extending parallel to the rows; each N-type well houses a...
7126855 Semiconductor device that enables simultaneous read and write/read operation  
A semiconductor device has a memory cell array having the arrangement of a plurality of cores, each of which comprises one block or a set of a plurality of blocks, each block defining a range of...
7126853 Electronic memory having impedance-matched sensing  
An electronic memory, typically a flash EPROM, contains an array of memory sections ( 40 ), each containing an array of memory cells ( 54 ). Global bit lines ( 60 ) fully traverse the memory. Local...
7123496 L0 cache alignment circuit  
A L0 cache is provided that includes a plurality of memory cells, full swing signal bit lines coupled to the plurality of memory cells to output full swing data signals, small signal global bit...
7120054 Preconditioning global bitlines  
A method and apparatus for discharging global bitlines in a flash memory to a voltage sufficiently low to avoid drain disturb for non-selected cells in a programming operation. A discharge device...
7110295 Semiconductor data processing device  
An erasing current is distributed to reduce a load of an internal power circuit and to decrease the number of drivers for erase. A semiconductor data processing device has: a memory array having...
7102941 Semiconductor memory device and portable electronic apparatus  
A semiconductor memory device including (A) a global line; (B) a memory array having (i) a local line, (ii) a decoder connected to the global line and the local line, and (iii) a memory block and a...
7095655 Dynamic matching of signal path and reference path for sensing  
A method for operating a non-volatile memory cell device, the method including providing an array of memory array cells connected to word lines and local bit lines, the local bit lines being...
7095652 Semiconductor storage device  
A semiconductor storage device comprises memory cells that store data by accumulating or releasing an electric charge; a memory cell array having a matrix arrangement of the memory cells; a...
7079417 Read-while-write flash memory devices having local row decoder circuits activated by separate read and write signals  
A flash memory device can include a local row decoder circuit that is configured to drive word lines coupled to a bank of a flash memory responsive to separate read and write control signals...
7072225 Nonvolatile memory and method of programming the same memory  
There is provided a method of programming a non-volatile memory which can solve the problem of the data write system of the existing flash memory that a load capacitance of bit lines becomes large,...
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