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8179719 Systems and methods for improving error distributions in multi-level cell memory systems  
A memory system includes a state set module that provides a first state set having a plurality of states, each being assigned to represent a particular data sequence, and a second state set having...
8179722 Page buffer circuit and nonvolatile memory device  
A page buffer circuit comprises a sense amplification unit configured to compare a reference voltage and a bit line voltage of a bit line of a selected memory block and to increase a voltage level...
8180981 Cache coherent support for flash in a memory hierarchy  
System and method for using flash memory in a memory hierarchy. A computer system includes a processor coupled to a memory hierarchy via a memory controller. The memory hierarchy includes a cache...
8174896 Nonvolatile memory device and method of operating the same  
A nonvolatile memory device comprises a page buffer unit, a counter, a program pulse application number storage unit, and a program start voltage setting unit. The page buffer is configured to...
8174892 Increased NAND flash memory read throughput  
A method of reading sequential pages of flash memory from alternating memory blocks comprises loading data from a first page into a first primary data cache and a second page into a second primary...
8174857 Efficient readout schemes for analog memory cell devices using multiple read threshold sets  
A method for data readout includes storing two or more candidate sets of read thresholds for reading from a memory device that includes a plurality of analog memory cells. A group of the memory...
8174888 Page-buffer and non-volatile semiconductor memory including page buffer  
In one aspect, a non-volatile memory device is provided which is operable in a programming mode and a read mode. The memory device includes a memory cell array which includes a plurality of...
8159882 Nonvolatile semiconductor memory device and memory system  
A semiconductor memory device executes a writing operation based on a first bit assignment pattern at the time of writing. The first bit assignment pattern is created such that pieces of x-bit...
8154923 Non-volatile memory and method with power-saving read and program-verify operations  
A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during read, and...
8154926 Memory cell programming  
One or more embodiments include programming, in parallel, a first cell to one of a first number of states and a second cell to one of a second number of states. Such embodiments include...
8154918 Method for page- and block based scrambling in non-volatile memory  
A method and system for programming and reading data with reduced read errors in a memory device. In one approach, date to be written to the memory device is scrambled using a first pseudo random...
8149622 Memory system having NAND-based NOR and NAND flashes and SRAM integrated in one chip for hybrid data, code and cache storage  
A memory system includes a NAND flash memory, a NOR flash memory and a SRAM memory on a single chip. Both NAND and NOR memories are manufactured by the same NAND manufacturing process and NAND...
8149621 Flash memory device and method of testing the flash memory device  
A flash memory device and a method of testing the flash memory device are provided. The flash memory device may include a memory cell array including a plurality of bit lines, a control unit...
8144516 Dynamic pass voltage for sense operation in a memory device  
Methods for sensing and memory devices are disclosed. One such method for sensing uses a dynamic pass voltage on at least one adjacent memory cell that is adjacent to a selected memory cell for...
8145855 Built in on-chip data scrambler for non-volatile memory  
A non-volatile memory in which data is randomized before being stored in the non-volatile memory to minimize data pattern-related read failures. Randomizing is performed using circuitry on the...
8139414 Source side asymmetrical precharge programming scheme  
A method for programming NAND flash cells to minimize program stress while allowing for random page programming operations. The method includes asymmetrically precharging a NAND string from a...
8134869 Semiconductor memory having electrically erasable and programmable semiconductor memory cells  
An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected...
8134870 High-density non-volatile read-only memory arrays and related methods  
In an embodiment, a read-only memory array includes a plurality of word lines, a plurality of bit-lines including first and second bit-lines, and a plurality of memory cells configured to...
8134872 Apparatus and methods for programming multilevel-cell NAND memory devices  
Methods and apparatus are provided. A first data value is read from a first memory cell and is stored. An attempt is made to add a second data value to the first memory cell. If the attempt to add...
8130589 Semiconductor memory device using only single-channel transistor to apply voltage to selected word line  
A semiconductor memory device has a memory cell array, a first transistor of a first conductivity type, a second transistor of a second conductivity type and a third transistor of the first...
8125828 Page buffer circuit with reduced size and methods for reading and programming data with the same  
A page buffer circuit with reduced size and methods for reading and programming data is provided. In the reading operation, the page buffer circuit reads out a data bit by alternatively using a...
8117375 Memory device program window adjustment  
In one or more embodiments, a memory device is disclosed as having an adjustable programming window having a plurality of programmable levels. The programming window is moved to compensate for...
8107294 Read mode for flash memory  
A method for reading a nonvolatile memory array including an array of memory cells, each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain...
8107287 Method of programming nonvolatile memory device  
A method of programming a nonvolatile memory device includes sequentially programming first to (n−1)th logical pages of all the physical pages of a first memory block of the memory blocks in...
8107291 Method of programming flash memory device  
A method of programming data in a flash memory device is disclosed. The memory device includes a memory cell array which in turn includes at least one block, and the block in turn includes a...
8102707 Non-volatile multilevel memory cells  
The present disclosure includes methods, devices, modules, and systems for operating non-volatile multilevel memory cells. One method embodiment includes assigning, to a first cell coupled to a...
8094500 Non-volatile memory and method with write cache partitioning  
A portion of a nonvolatile memory is partitioned from a main multi-level memory array to operate as a cache. The cache memory is configured to store at less capacity per memory cell and finer...
8094495 Nonvolatile memory device  
A nonvolatile memory device includes a data memory cell array having multi level memory cells divided into two groups, a write sequence memory cell array configured to store a write sequence...
8085588 Semiconductor device and control method thereof  
Systems and methods for programming data to a memory device (MD). The methods involve receiving the data at MD (100) from an external data source. MD includes a memory cell array (MCA) for storing...
8081522 Page buffer circuit for electrically rewritable non-volatile semiconductor memory device and control method  
Within a page buffer 14 which is coupled to a non-volatile memory cell array 10 and temporally stores data as the data with a predetermined page unit is written in and read out to/from the memory...
8081509 Non-volatile memory device and method of operation therefor  
In one embodiment, the non-volatile memory device includes a well of a first conductivity type formed in a substrate, and a first plurality of memory cell transistors connected in series to a bit...
8072835 Row address decoder and semiconductor memory device having the same  
A row address decoder includes a first main word line decoding unit decoding first and second row addresses to generate first to fourth main decoding signals. When a data storage test is...
8068365 Non-volatile memory device having configurable page size  
A flash memory device having at least one bank, where the each bank has an independently configurable page size. Each bank includes at least two memory planes having corresponding page buffers,...
8064251 Memory device and method having charge level assignments selected to minimize signal coupling  
A non-volatile memory device programs memory cells in each row in a manner that minimizes the coupling of spurious signals. A control logic unit programs the cells in a row using a set of bit...
8059460 Method of programming nonvolatile memory device  
A method of programming a nonvolatile memory device includes an inputting step for inputting program data to a first latch of each of page buffers, and inputting redundancy data to a second latch...
8054683 Semiconductor memory device including charge storage layer and control gate  
A semiconductor memory device includes a plurality of memory cells, signal lines, and a control unit. Each of the plurality of memory cells includes a charge storage layer. Each of the plurality...
8050101 Nonvolatile memory devices having erased-state verify capability and methods of operating same  
A program method of a nonvolatile memory device includes applying a program voltage to program cells for changing data; verifying the program cells, based on the changed data; and verifying...
8050090 Memory page boosting method, device and system  
A memory page boosting method, device and system for boosting unselected memory cells in a multi-level cell memory cell is described. The memory device includes a memory array of multi-level cell...
8050089 Multi-bit flash memory device and memory cell array  
A flash memory device includes a plurality of memory blocks. A selected memory block among the plurality of memory blocks includes 2n pages of data. The selected memory block includes different...
8045374 Erase verification method of flash memory by selectively assigning deselected sectors  
A suitable erase verification (ERSV) method of a flash memory apparatus is provided, which is different from the conventional ERSV method. That is, by managing the ERSV operation on the flash...
8045377 Non-volatile memory with dynamic multi-mode operation  
A method and system for extending the life span of a flash memory device. The flash memory device is dynamically configurable to store data in the single bit per cell (SBC) storage mode or the...
8036037 ***WITHDRAWN PATENT AS PER THE LATEST USPTO WITHDRAWN LIST***
Method of programming flash memory device
 
A method of programming data in a flash memory device is disclosed. The memory device includes a memory cell array which in turn includes at least one block, and the block in turn includes a...
8036030 Multi-level cell copyback program method in a non-volatile memory device  
A multi-level cell copyback program method in a non-volatile memory device is disclosed. The method includes performing a multi-level cell copyback program operation; performing selectively a...
8036042 Method of operating nonvolatile memory device  
A method of operating a nonvolatile memory device includes performing a reset operation for setting a level of a program voltage to a first level, performing a program operation and a verification...
8036041 Method for non-volatile memory with background data latch caching during read operations  
Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving...
8036034 Semiconductor storage device equipped with a sense amplifier for reading data and threshold-voltage-information data  
A semiconductor storage device comprises: a sense amplifier circuit; a first data retaining circuit and a second data retaining circuit configured to retain data and threshold voltage information,...
8024512 Memory controller and data processing system  
A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of...
8023325 Semiconductor memory having electrically erasable and programmable semiconductor memory cells  
An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected...
8004896 Method of controlling operation of flash memory device  
According to a method of controlling the operation of a flash memory device including a number of memory blocks, a memory block of the memory blocks is first selected as a reference block. A...
8004898 Nonvolatile memory device, program method thereof, and memory system including the same  
A nonvolatile memory device may include a memory cell array adapted to store tail-bit flag information indicating tail-bit memory cells, and a tail-bit controller adapted to calibrate a program...