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5530675 Floating gate nonvolatile memory with uniformly erased threshold voltage  
A method is described for eliminating overerasure in a nonvolatile memory that includes a plurality of memory cells, each having a control gate, a floating gate, a drain, and a source. The...
5526315 Biasing circuit and method to achieve compaction and self-limiting erase in flash EEPROMS  
The erasing method of this invention results in a relatively narrow distribution of threshold voltages when used to flash erase a group of floating-gate-type memory cells (10). Each cell includes...
5521864 Non-volatile semiconductor memory device allowing fast verifying operation  
A bit line reset transistor resets every second bit line of a plurality of bit lines to be write-verified. At this time, a transfer gate disconnects a column latch from the unreset bit line. Then,...
5519652 Nonvolatile semiconductor memory for positively holding stored data  
A semiconductor memory has a plurality of word lines, a plurality of bit lines, a plurality of memory cells, a differential sense amplifier, and load transistors. Each of the memory cells is a MIS...
5517453 Memory with multiple erase modes  
An electrically-erasable, electrically programmable read-only memory (EEPROM) with multiple erase modes identifies sections of memory cells that have not received a write operation subsequent to...
5508956 Nonvolatile flash-EEPROM memory array with source control transistors  
To reduce the number of depleted cells and the errors caused thereby, the memory array includes groups of control transistors corresponding to groups of memory cells. The control transistors of...
5493138 Single transistor non-volatile electrically alterable semiconductor memory device  
An improved electrically programmable and erasable memory device having a plurality of addressable single transistor cells, each transistor having spaced source and drain regions, a floating gate...
5491656 Non-volatile semiconductor memory device and a method of using the same  
An electrically alterable non-volatile semiconductor memory. The memory cells are formed in a matrix of columns and rows. A row decoder and column decoder are provided to select one of the row...
5491660 On-chip operation control for memories  
The memory control this invention includes a microprogram-read-only-memory (CROM) containing micro instructions for operation of an integrated-circuit memory, a program counter multiplexer (PCM)...
5490110 Non-volatile semiconductor memory device having disturb verify function  
The electrically rewritable nonvolatile semiconductor memory device includes a plurality of memory cells arranged in rows and columns, a decoder circuit for selecting at least one of the plurality...
5483494 Nonvolatile semiconductor memory device having a reduced delay in reading data after changing from standby to an operation mode  
A nonvolatile memory device includes a matrix array of transistors. A read potential generation circuit provides a potential to a selected transistor and generates a read potential in accordance...
5483485 Nonvolatile semiconductor system with automatic over erase protection  
The present invention has an object to prevent an overerasing in a flash EEPROM. In memory transistors (1)-(4), the source line SL is set at Vpp and word line WL1 and WL2 are set at a...
5477499 Memory architecture for a three volt flash EEPROM  
A flash EEPROM array includes a plurality of flash EEPROM cells and the flash EEPROM array has both a low power supply voltage VCC and high speed performance. This high speed performance is...
5475634 Floating gate memory array with latches having improved immunity to write disturbance, and with storage latches  
An electrically programmable and erasable floating gate memory device has two substantially identical sections. Each section has a plurality of column address lines, a plurality of row lines and a...
5475249 Nonvolatile semiconductor device to erase with a varying potential difference  
Erasing operation can be carried out by applying a given potential difference between the control gate electrodes and the source regions in memory transistors 1a-1d by a potential difference...
5473564 Memory card having an integrated circuit for the secure counting down of units  
In a memory card designed to count down a number of units by successive programming of non-volatile, electrically erasable and electrically programmable memory cells, the memory is organized into...
5469444 Electrically erasable and programmable non-volatile memory system with write-verify controller using two reference levels  
An EEPROM includes an array of memory cell transistors, which is divided into cell blocks each including NAND cell units of series-connected cell transistors. A sense amplifier is connected to bit...
5467306 Method of using source bias to increase threshold voltages and/or to correct for over-erasure of flash eproms  
The method of this invention allows use of a smaller wordline voltage Vp1 during programming. In addition, the method results in a relatively narrow distribution of threshold voltages Vt when used...
5463587 Nonvolatile semiconductor system  
It is an object of the present invention to optimize the range of threshold voltage in a flash EEPROM and to simplify the verifying operation. In memory transistors (1)-(4) and a dummy memory...
5457652 Low voltage EEPROM  
A non-volatile memory system which includes an array of memory cells with each of the cells including a source, drain and intermediate channel and which is suitable for low voltage operation such...
5444655 Non-volatile semiconductor memory device with a small distribution width of cell transistor threshold voltage after erasing data  
A semiconductor memory device includes a silicon chip, a memory cell transistor formed in the chip, a charge pump circuit formed in the chip, for boosting a source potential to generate a boosted...
5432730 Electrically programmable read only memory array  
There is provided an EPROM array including columns of EPROM cells, three types of diffusion bit lines, two types of metal lines and two types of select transistors. The metal lines are formed of...
5430675 An EEPROM Circuit, a memory device having the EEPROM circuit and an IC card having the EEPROM circuit  
In an EEPROM, source electrodes S of memory cell transistors MT1 to MTn are grounded, via transistors MG1 to MGn. The source electrodes S are separated from each other so as to maintain the source...
5428568 Electrically erasable and programmable non-volatile memory device and a method of operating the same  
In a programming mode of operation of a flash type non-volatile semiconductor memory device, an erase voltage pulse is applied a memory cell to bring the memory cell into an erased state. Then, an...
5426611 Non-volatile semiconductor device  
When each of memory transistors 1-4 is to be selected for erasure, word lines WL1 and WL2 are set at GND level, source lines SL1 and SL2 are set at high-potential level, and bit lines BL1 and BL2...
5422843 Method of erasing information in memory cells  
A method of this invention is applied to a nonvolatile memory device composed of first memory cells connected to one of a first word-line pair and second memory cells connected to the other of the...
5422846 Nonvolatile memory having overerase protection  
A nonvolatile memory (20) includes an array of floating gate transistors (22) organized as rows and columns. Word lines of adjacent rows are coupled together to form shared word lines. In one...
5416738 Single transistor flash EPROM cell and method of operation  
A flash EPROM memory cell array includes a plurality of flash cells arranged as a matrix of rows in columns of said cells. Each cell includes a single transistor. For each row of flash cells in...
5412609 Nonvolatile semiconductor memory device  
Word lines are divided into a plurality of blocks in a row direction, and divided into a plurality of sections having e.g., four word lines in a column direction. An area where each block and each...
5410511 Methods of controlling the erasing and writing of information in flash memory  
In a flash memory, the value of an erasing voltage pulse is temporarily set so that information stored in all the memory cells is erased by means of the erasing voltage pulse. The value of the...
5408429 Method of altering a non-volatile semiconductor memory device  
A method for writing data to a selected EEPROM memory cell and erasing data in a selected EEPROM memory cell. During writing of the EEPROM memory cell, a tunnel effect is used to draw charges from...
5406521 Semiconductor memory device and data erase method for it  
A semiconductor memory device comprises a plurality of word lines (WL1, WL2), a plurality of bit lines (BL1, BL"), a plurality of memory cells (MC11, MC12) each includes a transistor (9) formed on...
5402382 Nonvolatile semiconductor memory device capable of erasing by a word line unit  
A nonvolatile semiconductor memory device has a plurality of memory cells, which are arranged in a matrix form having rows and columns and each have floating a gate for holding an information...
5402383 Electrically erasable non-volatile semiconductor memory device for selective use in boot block type or normal type flash memory devices  
An electrically erasable non-volatile semiconductor memory device has a memory cell array, a first erase unit, a second erase unit, and an operation mode establish unit. The erasing operation of...
5400286 Self-recovering erase scheme to enhance flash memory endurance  
Word line stress is used to narrow the distribution of threshold voltages after an erase of an array of memory cells. One embodiment of the invention provides a method for erasing an array...
5400276 Electrically erasable nonvolatile semiconductor memory that permits data readout despite the occurrence of over-erased memory cells  
The purpose of the present invention is to provide an electrically erasable nonvolatile semiconductor memory that permits correct data readout despite the occurrence of over-erased memory cells....
5398202 Reprogrammable nonvolatile semiconductor memory formed of MOS transistors and reprogramming method thereof  
A reprogramming method of a nonvolatile semiconductor memory formed of MOS transistor cells is provided. Data values are written to transistors of one of groups which is obtained by dividing the...
5396459 Single transistor flash electrically programmable memory cell in which a negative voltage is applied to the nonselected word line  
A nonvolatile semiconductor memory using a single floating gate transistor, wherein a control gate elecrrode is negatively biased while a source region is positively biased, and a writing...
5388070 Storage arrangement and method for operating the arrangement  
The optimum programming voltage in programmable storage arrangements such as EPROMs and notably EEPROMs is dependent on manufacturing tolerances which are difficult to determine from the outside....
5384743 Structure and method for flash eprom memory erasable by sectors  
A device for the erasure of sectors of a flash EPROM memory map comprises routing means to apply an erasing voltage to several sectors selected simultaneously by a predetermined resistor for all...
5384742 Non-volatile semiconductor memory  
A memory cell array is divided into a plurality of blocks. In altering data for a block (selected block), a moderating voltage is applied to the source or control gate of a memory cell in another...
5379256 Electrically erasable programmable read-only memory with write/verify controller  
A plurality of electrically erasable programmable read-only memories or EEPROMs are associated with a controller LSI. Each EEPROM includes an array of floating-gate tunneling memory cell...
5377147 Method and circuitry for preconditioning shorted rows in a nonvolatile semiconductor memory incorporating row redundancy  
Circuitry for verifying the preconditioning of shorted cells within a flash memory cell. The preconditioning circuitry accommodates shorted cells, allowing them to pass verification at lower...
5371706 Circuit and method for sensing depletion of memory cells  
The circuit and method of this invention provide for rapid and reliable detection of depleted or nearly-depleted cells in a column. The circuit is formed on the substrate of a nonvolatile,...
5371705 Internal voltage generator for a non-volatile semiconductor memory device  
The semiconductor device includes a voltage generator for generating selectively a signal of a first level or a second level onto a first supply line, and a voltage converter using voltage signals...
5365484 Independent array grounds for flash EEPROM array with paged erase architechture  
An improved architecture for an array of flash EEPROM cells with paged erase is provided. The array is formed of a plurality of half-sectors. In each sector, the sources of the memory cell...
5359555 Column selector circuit for shared column CMOS EPROM  
A CMOS memory is disclosed which employs a column selector circuit that prevents write disturb in shared column EPROMs. When a selected memory transistor is programmed, disturb is prevented by...
5359558 Flash eeprom array with improved high endurance  
An improved over-erased bit correction structure is provided for performing a correction operation on over-erased memory cells in an array of flash EEPROM memory cells after erase operation so as...
5357476 Apparatus and method for erasing a flash EEPROM  
A flash EEPROM array (22) is erased and a threshold voltage distribution of the erased flash EEPROM cells (36, 39-46) is converged to within a predetermined voltage range by using a two-step...
5357465 Single transistor EEPROM memory cell  
A single-transistor non-volatile memory cell MOS transistor with a floating gate and a control gate using two levels of polysilicon and a tunnel dielectric that overlaps the drain area wherein a...