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7542344 Non-volatile memory device and self-compensation method thereof  
A non-volatile memory device includes a memory cell array at least one block having a plurality of memory cells, and at least one reference cell with respect to each block, an X decoder and a Y...
7539053 Non-volatile semiconductor memory device  
A non-volatile semiconductor memory device includes plurality of word lines and a plurality of bit lines comprising even numbered bit lines and odd numbered bit lines and a memory cell array...
7535761 Flash memory device capable of preventing coupling effect and program method thereof  
The present invention provides a flash memory device that includes a word line; even page cells that are physically adjacent and connected to the word line; and odd page cells that are physically...
7532512 Non-volatile memory device and method of handling a datum read from a memory cell  
A memory device includes a pre-charge transistor for connecting/disconnecting the input line of a global data line driver to a supply voltage line. To reduce the flow of current through the...
7532514 Non-volatile memory and method with bit line to bit line coupled compensation  
When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it...
7532510 Flash memory device with sector access  
A flash memory includes memory cell array having memory cells divided into sectors, a page buffer block having groups of page buffers corresponding to the sectors, and a page buffer controller...
7525839 Semiconductor memory device capable of correcting a read level properly  
In a memory cell array, a plurality of memory cells each of which stores a plurality of bits are connected to a plurality of word lines and a plurality of bit lines and are arranged in a matrix....
7525842 Increased NAND flash memory read throughput  
A method of reading sequential pages of flash memory from alternating memory blocks comprises loading data from a first page into a first primary data cache and a second page into a second primary...
7525845 Non-volatile semiconductor storage device  
In a memory cell array which is constituted with flash memory, a pair of a positive memory cell and a negative memory cell, to which data with mutually opposite values are written, is plurally...
7518909 Non-volatile memory device adapted to reduce coupling effect between storage elements and related methods  
A non-volatile semiconductor memory device comprises first and second sub-memory arrays and a strapping line disposed between the first and second sub-memory arrays. A programming operation of the...
7518945 Page buffer circuit of flash memory device  
A page buffer circuit of a flash memory device includes a plurality of page buffers connected to a predetermined number of bit lines, respectively, and also connected to a Y-gate circuit, the page...
7512005 NAND memory with side-tunneling  
A string of nonvolatile memory cells are formed with control gates extending between floating gates, control gates and floating gates separated by tunnel dielectric layers. Electron tunneling...
7512012 Non-volatile memory and manufacturing method and operating method thereof and circuit system including the non-volatile memory  
The memory cell includes a first unit, a semiconductor layer, a second unit, and a doped region. The first unit includes a first gate, a first charge trapping layer, and a second charge trapping...
7508711 Arrangements for operating a memory circuit  
In one embodiment a method for programming memory cells is disclosed. The method can include applying a programming voltage to a selected memory cell during a lower page programming procedure, the...
7508709 Page buffer circuit with reduced size and methods for reading and programming data with the same  
A page buffer circuit with reduced size and methods for reading and programming data is provided. In the reading operation, the page buffer circuit reads out a data bit by alternatively using a...
7505315 Nonvolatile semiconductor storage apparatus  
A nonvolatile semiconductor storage apparatus comprises a memory cell array having a plurality of memory cells which are connected to word lines and to bit lines and in each of which different...
7505318 Nonvolatile semiconductor memory device  
A nonvolatile semiconductor memory device of the present invention is characterized in that, when data is written to a flag cell area, every other flag cell in the direction of one bit line BL...
7505312 Nonvolatile semiconductor memory device capable of controlling proximity effect due to coupling between adjacent charge storage layers  
There is disclosed a semiconductor integrated circuit device including a memory cell array having a plurality of blocks, a first non-volatile semiconductor memory cell which is arranged in the...
7499324 Non-volatile memory and method with control gate compensation for source line bias errors  
Source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the source of a memory cell is erroneously biased by a voltage drop...
7499323 Flash memory device and data I/O operation method thereof  
A flash memory device comprises a memory cell array, an input buffer unit, an output driver unit, a first page buffer unit, a second page buffer unit, a first data I/O unit, and a second data I/O...
7499332 Circuit and method for electrically programming a non-volatile semiconductor memory via an additional programming pulse after verification  
A method of electrically programming a memory cell includes: applying at least one electrical programming pulse to the memory cell; verifying the reaching of a target programming state by the...
7499326 Apparatus for reducing the impact of program disturb  
The unintentional programming of an unselected (or inhibited) non-volatile storage element during a program operation that intends to program another non-volatile storage element is referred to as...
7495968 Wired-or typed page buffer having cache function in a nonvolatile memory device and related method of programming  
Disclosed is a page buffer having a wired-OR type structure and a cache function which is adapted for use in a nonvolatile semiconductor memory device and a method of programming same. The page...
7486558 Non-volatile memory with managed execution of cached data  
Methods and circuitry are present for executing current memory operation while other multiple pending memory operations are queued. Furthermore, when certain conditions are satisfied, some of...
7486566 Methods, apparatus, and systems for flash memory bit line charging  
Various embodiments include a circuit to receive data information, a memory array including memory cells coupled to a bit line, and control circuitry to charge the bit line while the data...
7483301 Nonvolatile memory devices that support virtual page storage using odd-state memory cells and methods of programming same  
A nonvolatile memory array includes first and second blocks of three-state memory cells therein. These first and second blocks are configured to operate individually as first and second blocks of...
7477550 NAND flash memory device and method of improving characteristic of a cell in the same  
A non-volatile memory device includes a memory cell array, a page buffer, a cell characteristic detecting circuit, an X decoder and a Y decoder. The memory cell array has memory cells coupled to...
7471576 Method of transferring data in an electrically programmable memory  
A method is provided for transferring data in a memory that includes memory cells forming memory pages, and a page buffer that includes a register, with signal lines selectively transferring data...
7463521 Method for non-volatile memory with managed execution of cached data  
Methods and circuitry are present for executing current memory operation while other multiple pending memory operations are queued. Furthermore, when certain conditions are satisfied, some of...
7463520 Memory device with variable trim settings  
A memory device includes a memory array including a plurality of cells. The cells are divided into a plurality of subsets. Each subset has at least one associated trim parameter. The trim...
7460401 Method for checking block erasing of a memory and circuit thereof  
A method checks the state of a set of memory cells of a memory having memory cells arranged in a memory array, row and column decoders for selecting a memory cell, and a sense amplifier for...
7453734 Method and apparatus for fast programming of memory  
Methods and apparatuses are disclosed for programming a page of nonvolatile memory cells across multiple nonvolatile memory cells accessed by multiple word lines.
RE40567 Flash memory device of capable of sensing a threshold voltage of memory cells on a page mode of operation  
A method for determining data stored by a memory cell. The memory cell has a select gate coupled to a wordline, a first electrode coupled to a bitline, and a second electrode coupled to a...
7447096 Method for refreshing a non-volatile memory  
A non-volatile memory and a method of refreshing a memory are described. The method includes allowing an external system to control refreshing operations within the memory. The memory may generate...
7447070 Highly compact non-volatile memory and method therefor with internal serial buses  
A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple...
7443725 Floating gate isolation and method of making the same  
The present invention relates to a method for forming a set of floating gates which are isolated from each other by means of slits, as well as semiconductor devices using the floating gate. The...
7423915 Random cache read using a double memory  
A non-volatile memory, such as a Flash memory, is configured to perform a random multi-page read operation. The memory may include a core array of non-volatile memory cells and input lines for...
7411820 Three-level nonvolatile semiconductor memory device and associated method of operation  
A nonvolatile semiconductor memory device comprises a memory array of 3-level nonvolatile memory cells. The memory array comprises first even and odd strings of memory cells connected to...
7408819 Semiconductor memory device with a page buffer having an improved layout arrangement  
A memory device is provided. The memory device includes a matrix of memory cells adapted to store data and arranged in a plurality of bit lines, the bit lines extending along a first direction; a...
7405974 Semiconductor memory device, page buffer resource assigning method and circuit therefor, computer system and mobile electronic device  
A semiconductor memory device includes a page buffer circuit and an arrangement of memory elements each including: a gate electrode provided on a semiconductor layer with an intervening gate...
7400534 NAND flash memory and data programming method thereof  
A semiconductor integrated circuit device includes even-numbered bit lines, odd-numbered bit lines, cell source lines, first memory elements electrically connected between the even-numbered bit...
7391645 Non-volatile memory and method with compensation for source line bias errors  
Source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the source of a memory cell is erroneously biased by a voltage drop...
7385850 Method of programming and verifying cells of a nonvolatile memory and relative NAND FLASH memory  
A method of programming cells in a nonvolatile memory is based upon a Global Verify operation and a Byte-by-byte Verify operation. The cells of a destination page of the nonvolatile memory are...
7379333 Page-buffer and non-volatile semiconductor memory including page buffer  
In one aspect, a non-volatile memory device is provided which is operable in a programming mode and a read mode. The memory device includes a memory cell array which includes a plurality of...
7379337 Flash memory device and read operation method thereof  
A flash memory device having a function of selectively changing a precharge voltage for a sensing node and a read operation method thereof. The flash memory device includes a memory cell array, a...
7372744 Memory system which copies successive pages, and data copy method therefor  
A memory system includes a memory cell array, a bit line switch, first and second page buffers, a column switch, an error correction circuit, and control circuits. The second page buffer can swap...
7366017 Method for modifying data more than once in a multi-level cell memory location within a memory array  
A method and apparatus for programming one or more bits in an upper page twice depending on the value in a corresponding bit in a corresponding lower page in a multi-level cell device. The method...
7366014 Double page programming system and method  
A method for programming an electrically programmable memory including a plurality of memory cells arranged in individually-selectable memory cell sets each including at least one memory cell. The...
7353326 Flash memory device supporting cache read operation  
A flash memory device comprises a non-volatile memory core operatively connected to first and second buffer memories through a page buffer. The device further comprises a first register adapted to...
7349257 Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations  
A combination EEPROM and Flash memory is described containing cells in which the stacked gate transistor of the Flash cell is used in conjunction with a select transistor to form an EEPROM cell....