Matches 151 - 200 out of 255 < 1 2 3 4 5 6 >
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5097449 Non-volatile memory structure  
A non-volatile memory circuit for use with an E 2 PROM includes redundant, parallel connected, floating node MOSFET memory cells for storing complementary information. The non-volatile memory...
H001035 Non-volatile analog memory circuit with closed-loop control  
A non-volatile analog memory circuit includes charge depositing and storing ircuitry, voltage sensing circuitry, and closed-loop control circuitry. The charge depositing and storing circuitry...
5088066 Redundancy decoding circuit using n-channel transistors  
Four n-channel transistor, single-stage XNOR/XOR decoding circuit provides for an improved performance of a decoding circuit using CAMs to access redundant memory.
5078498 Two-transistor programmable memory cell with a vertical floating gate transistor  
A two-transistor programmable memory cell (FIG. 1A, 20) with one vertical floating gate transistor (VT) and one planar transistor (PT)--the planar transistor can be optimized for programming with...
5055897 Semiconductor cell for neural network and the like  
A cell employing floating gate storage device particularly suited for neural networks. The floating gate from the floating gate device extends to and becomes part of a second, field effect device....
5053638 Semiconductor neural circuit device having capacitive coupling and operating method thereof  
A neural circuit device modeled on vital cells includes a plurality of first signal lines to which signals to be computed are transferred, a plurality of amplifiers serving as the bodies of the...
5049758 Adaptable CMOS winner-take all circuit  
An integrated circuit amplifier having a random input offset voltage is adaptable such that the input offset voltage may be cancelled out. An inverting input node is a floating input node and is...
5043941 Non-volatile memory  
A non-volatile memory provides a signal hold circuit which uses a FAMOS instead of an input transistor of a ratiod inverting amplifier and outputs a change in a threshold value of the FAMOS, for...
5028810 Four quadrant synapse cell employing single column summing line  
The present invention covers a synapse cell for providing a weighted connection between a differential input voltage and a single output summing line having an associated capacitance. The...
5027171 Dual polarity floating gate MOS analog memory device  
A dual-polarity nonvolatile MOS analog memory cell is disclosed that comprises two pairs of complementary metal oxide field effect transistors. Each pair includes a p-channel and an n-channel...
5021999 Non-volatile semiconductor memory device with facility of storing tri-level data  
A non-volatile memory cell includes a MOS transistor of double gate construction. The MOS memory transistor includes a floating gate structure which includes electrically separated first and second...
5016217 Logic cell array using CMOS EPROM cells having reduced chip surface area  
An Electrically Programmable Read Only Memory (EPROM) memory cell includes a serially connected Complementary Metal Oxide Silicon (CMOS) transistor pair having common floating gates and common...
5012446 Large-scale EPROM memory with a high coupling factor  
An electrically programmable non-volatile memory comprises an array of word lines (LM2) extending along rows, connecting the control gates of floating gate transistors, and an array of bit lines...
5005155 Optimized electrically erasable PLA cell for minimum read disturb  
A four device cell for an electrically erasable programmable logic device includes a floating gate tunnel device (sometimes referred to as a tunnel capacitor), a floating gate read transistor...
4982377 Erasable programmable read only memory device improved in operation speed and in the amount of read out current  
An erasable programmable read only memory device includes a plurality of memory cells arranged in rows and columns, a plurality of word lines associated with the rows of the memory cells,...
4963769 Circuit for selective power-down of unused circuitry  
A power reduction circuit for selectively providing power to circuitry associated with and coupled to the power reduction circuit, which includes two transistors having current paths coupled in...
4935702 Subthreshold CMOS amplifier with offset adaptation  
An integrated circuit amplifier having a random input offset voltage is adaptable such that the input offset voltage may be cancelled out. An input node is a floating input node and is coupled to a...
4935648 Optimized E.sup.2 pal cell for minimum read disturb  
A four device cell is disclosed for an electrically erasable programmable logic device. The four devices include a floating gate tunnel capacitor, a floating gate read transistor having its...
4885719 Improved logic cell array using CMOS E.sup.2 PROM cells  
A programmable memory cell useful in a logic cell array draws no D.C. power in either a "1" or a "0" state. The cell includes a CMOS transistor pair including a p-channel transistor connected to a...
4866307 Integrated programmable bit circuit using single-level poly construction  
A zero-power bit circuit comprised in part of a pair of single-level poly transistors having opposite impurity-type channels, the pair connected to accomplish the programming function of a...
4858185 Zero power, electrically alterable, nonvolatile latch  
A compact, nonvolatile, zero static power, electrically alterable, bistable CMOS latch device is fabricated with single layer of polysilicon. The single polysilicon layer forms the floating gates...
4852063 Programmable voltage offset circuit  
A programmable voltage offset circuit (PVOC) (1) comprises a temporary latch memory (7); a latch disable circuit (5) which selects that PVOC (1) among several such circuits which may be...
4835741 Frasable electrically programmable read only memory cell using a three dimensional trench floating gate  
An electrically programmable read only memory device formed in a face of a semiconductor substrate which includes a floating gate transistor having a floating gate and a control gate formed at...
4829203 Integrated programmable bit circuit with minimal power requirement  
A zero-power programmable bit circuit comprised of a programmable-inverter means with an isolation transistor and with an inverter-buffer. The programmable-inverter means is includes at least one...
4823316 Eeprom memory cell with a single polysilicon level and a tunnel oxide zone  
The memory cell comprises a selection transistor, pickup transistor and a tunnel condenser formed using a single layer of polysilicon. The tunnel condenser is formed on an active area distinct and...
4823320 Electrically programmable fuse circuit for an integrated-circuit chip  
A fuse circuit for an integrated circuit chip which includes a non-volatile memory element, a circuit programmer for the memory element, and a read circuit for detecting the programmed states of...
4807003 High-reliablity single-poly eeprom cell  
The present invention provides a single-poly electrically erasable programmable read only memory device which is formed in a semiconductor substrate of a first conductivity type. The memory device...
4800528 Non-volatile memory having charge correction circuitry  
A semiconductor device having one or more first non-volatile memory transistors and a detector having a second non-volatile memory transistor with which a charge level written in the first...
4788663 Nonvolatile semiconductor memory device with a lightly-doped drain structure  
Each memory cell in an EPROM includes two memory cell transistors which share a common floating gate and have two separated drains, one of which is connected to a read bit line and the other of...
4785199 Programmable complementary transistors  
Programmable logic gate structures employ pairs of complementary transistors. Programming of the transistors is accomplished either by voltage biasing a shared floating gate of a CMOS transistor...
4780750 Electrically alterable non-volatile memory device  
In this invention, an Electrically Alterable Non-Volatile Memory (EANOM) cell is disclosed. The EANOM ceil comprises an MOS transistor, having a source, a gate and a drain. The EANOM cell also has...
4774202 Memory device with interconnected polysilicon layers and method for making  
A memory device, based upon a field effect transistor having a floating gate is constructed for use in a silicon integrated circuit array of similar memory devices. The memory device includes only...
4769788 Shared line direct write nonvolatile memory cell array  
A memory array comprised of floating gate, direct write nonvolatile memory cells having cell interiors which are interconnected by successive adjacent rows to share column lines between adjacent...
4766473 Single transistor cell for electrically-erasable programmable read-only memory and array thereof  
A single transistor EEPROM cell comprises a source, a channel, a drain, a floating gate and a control gate. The control gate and the floating gate are co-extensive over the channel. Programming is...
4748593 High speed nonvolatile memory cell  
The circuit and structure of a direct write differential nonvolatile memory cell. The features of the cell include high speed read sensing, write without a prior erase operation, single polysilicon...
4742492 EEPROM memory cell having improved breakdown characteristics and driving circuitry therefor  
Erasable programmable memory cell having a control gate, a row line and bit line is disclosed. Line driving circuitry coupled to the bit line and control gate applies a negative voltage to the bit...
4736342 Method of forming a field plate in a high voltage array  
An array of electrically programmable semiconductor memory cells of a type having electrically conducting odd and even row lines, left and right column and ground lines and field oxide regions...
4725980 Read only memory circuit  
A ROM circuit is used in place of a conventional fuse type ROM which is incorporated in a semiconductor integrated circuit network together with other circuit blocks on a chip. The ROM circuit...
4718041 EEPROM memory having extended life  
Disclosed is a method and apparatus for extending the programmable life of an EEPROM memory. For each write commamd generated external to the memory an automatic internal read operation is...
4715014 Modified three transistor EEPROM cell  
An electrically erasable programmable semiconductor memory cell having an associated conducting column line, read/write line, sense line and row line includes a floating gate transistor which...
4713677 Electrically erasable programmable read only memory cell including trench capacitor  
An EEPROM cell is described which includes a trench formed in the field oxide adjacent to the EEPROM cell. Both the control gate and the floating gate of the cell are formed over this trench. By...
4709255 Semiconductor device comprising a non-volatile storage transistor  
A non-volatile storage cell has a floating conductive layer which is coupled to an injector region which is located in the semiconductor body and, viewed on the surface, is connected by a...
4706220 Non-volatile RAM cell with dual high voltage precharge  
A non-volatile memory cell circuit for storing and recalling a digital signal, the memory cell circuit having a store cycle having a repeating series of recurring store cycle sequences; each store...
4686652 Non-volatile RAM cell with single high voltage precharge  
A memory cell circuit for storing the state of a digital signal on a data bus in response to an address signal. The memory cell has a store cycle with a repeating series of recurring store cycle...
4685085 Non-volatile ram cell with charge pumps  
A random access memory cell includes a volatile RAM cell, a non-volatile RAM cell and a transfer control circuit connected between the volatile and non-volatile elements. The volatile element...
4683554 Direct write nonvolatile memory cells  
A floating gate type nonvolatile memory cell of the general class known as electrically erasable programmable read only memories, configured with a single polysilicon layer, operable in a direct...
4672580 Memory cell providing simultaneous non-destructive access to volatile and non-volatile data  
A memory cell providing separate storage of volatile and non-volatile data. The volatile and non-volatile data elements, which are not necessarily duplicative, can be non-destructively accessed...
4668970 Semiconductor device  
In a semiconductor device which includes an insulation film through which a charge can tunnel, a gate insulation film of a material different from the material of said insulation film or having a...
4663740 High speed eprom cell and array  
A high speed EPROM cell comprises two floating gate field effect transistors and one field effect transistor. One of the floating gate transistors is smaller than the other floating gate transistor...
4661833 Electrically erasable and programmable read only memory  
An electrically erasable and programmable read only memory comprises a semiconductor substrate of a first conductivity type, source and drain regions both of a second conductivity type formed in...
Matches 151 - 200 out of 255 < 1 2 3 4 5 6 >