Matches 101 - 150 out of 255 < 1 2 3 4 5 6 >
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5680346 High-speed, non-volatile electrically programmable and erasable cell and method  
A non-volatile programmable circuit having programming and read bitlines, a non-volatile memory cell, and a read select transistor, and a method for its operation. The non-volatile memory cell is...
5675162 EPROM, flash memory with high coupling ratio  
A semiconductor device is formed on a substrate lightly doped with a dopant, a source region and a drain region in the substrate on the surface thereof, a dielectric layer deposited upon the...
5652447 Flash EEPROM memory with reduced column leakage current  
A flash EEPROM having reduced column leakage current suitably includes cells with more uniform erase times arranged in an array. An intermediate n+ implant immediately following the DDI implant...
5644532 Method for programming a cell in a source-coupling, split-gate, virtual ground flash EEPROM array  
A selected cell in a virtual-ground flash EEPROM array, which is based on a source-coupled, split-gate storage cell, is programmed by grounding the source bit line of the selected cell, grounding...
5640346 Electrically programmable memory cell  
An EPROM cell comprises an MOS device including a floating gate electrode overlying, and ohmically insulated from, the channel region of the MOS device, and a separate diode including a p-n...
5633518 Nonvolatile reprogrammable interconnect cell with FN tunneling and programming method thereof  
An array of programmable interconnect cells, each cell having a floating gate as the gate of an MOS switch transistor which programmably connect or disconnects nodes, is used in an FPGA. The...
5625211 Two-transistor electrically-alterable switch employing hot electron injection and fowler nordheim tunneling  
An electrically-alterable switch includes a floating gate EEPROM transistor having a source, a drain, a control gate, and a floating gate. A select transistor includes a source capacitively coupled...
5617352 Non-volatile, bidirectional, electrically programmable integrated memory element implemented using double polysilicon  
A non-volatile, bidirectional electrically programmable integrated memory ement is describe which includes a dielectric structure supported by a substrate and a programming terminal supported by...
5604700 Non-volatile memory cell having a single polysilicon gate  
A non-volatile memory cell (10) is provided employing two transistors (11, 12) connected in series. A floating gate structure (13), formed with a single polysilicon deposition, is shared by each...
5596524 CMOS memory cell with gate oxide of both NMOS and PMOS transistors as tunneling window for program and erase  
A CMOS memory cell including a PMOS transistor and an NMOS transistor having a common floating gate with a gate oxide region of both the NMOS and PMOS transistors providing a tunneling window for...
5594687 Completely complementary MOS memory cell with tunneling through the NMOS and PMOS transistors during program and erase  
Circuitry added to CMOS memory cell configured to enable tunneling through its PMOS and NMOS transistors, the circuitry preventing leakage current during programming. The circuitry includes a...
5587945 CMOS EEPROM cell with tunneling window in the read path  
A CMOS memory cell including PMOS and NMOS transistors with a common floating gate. The CMOS memory cell includes a first capacitor connecting a first control voltage to the common floating gate...
5576568 Single-transistor electrically-alterable switch employing fowler nordheim tunneling for program and erase  
A one-transistor, electrically-alterable switch in combination with a pass transistor includes a first MOS transistor having a drain, a gate, and a source, and a pass transistor having a drain, a...
5570314 EEPROM devices with smaller cell size  
An EEPROM and method for making the same, having precisely shaped field oxide regions and memory cells, to provide improved electrical operating characteristics and increased memory density. A...
5557566 Semiconductor nonvolatile ram having E2PROM with a floating gate located above the midportion of the transistor channel  
A semiconductor nonvolatile RAM having a dynamic RAM cell and an E 2 PROM cell. The dynamic RAM cell includes a first transistor having a current path having one end connected to a bit line and a...
5515320 Non-volatile memory  
The non-volatile memory includes (A) a cell array including (a) memory cells arranged to form rows and columns, each cell having first and second transistors which commonly have a floating gate,...
5511036 Flash EEPROM cell and array with bifurcated floating gates  
Each unit cell (10) of a flash EEPROM array (50) includes a source (18), a drain (20) and a channel (22) formed in a substrate (12). A thin tunnel oxide layer (32) is formed over the substrate (12)...
5481492 Floating gate injection voltage regulator  
A circuit for regulating floating gate injection voltage comprises a volt regulator electrically coupled to a floating gate device. The floating gate device includes an electrically conductive...
5465231 EEPROM and logic LSI chip including such EEPROM  
Disclosed is an EEPROM cell which can be manufactured with ease by the standard CMOS process. The EEPROM cell of the present invention has a first MOS transistor formed in a semiconductor substrate...
5457771 Integrated circuit with non-volatile, variable resistor, for use in neuronic network  
Integrated circuit with a non-volatile variable resistor which is particularly adapted for use in a neuronic network. The integrated circuit comprises a symmetrically replicated structure including...
5436480 Integrated circuit interconnection programmable and erasable by a plurality of intersecting control traces  
A programmable interconnection of an integrated circuit including a floating gate having a portion thereof sandwiched in between a X-control trace and a Y-control trace. Another portion of the...
5432106 Manufacture of an asymmetric non-volatile memory cell  
An EPROM memory cell and its fabrication are described. The semiconductor substrate is a first conductivity type. The process begins by forming a conductive gate overlying the substrate, but...
5430674 Method and apparatus for sequential programming of a flash EEPROM memory array  
An integrated circuit arrangement for providing programming voltages to a flash EEPROM memory array including an arrangement for selecting only bits of a word which are to be programmed and...
5428571 Data latch circuit having non-volatile memory cell equipped with common floating gate and stress relaxing transistor  
A data latch circuit comprises a non-volatile memory cell having its threshold voltage changed in accordance with data to be stored therein, and a latch circuit. The cell has a transistor for...
5422504 EEPROM memory device having a sidewall spacer floating gate electrode and process  
An EEPROM memory array includes a plurality of memory cells having a floating gate electrode (22) formed as a sidewall spacer adjacent to a control gate electrode (20). Source and drain regions...
5414693 Self-aligned dual-bit split gate (DSG) flash EEPROM cell  
An EEPROM cell structure includes two floating gate transistors separated by a select gate transistor with the select transistor being shared by the two floating gate transistors in programming,...
5412603 Method and circuitry for programming floating-gate memory cell using a single low-voltage supply  
The drain-to-source voltage and current for programming a selected nonvolatile memory cell 10 are achieved efficiently by pumping the source 11 of a selected cell 11 to a voltage less than the...
5412599 Null consumption, nonvolatile, programmable switch  
A null consumption CMOS switch which may be set by nonvolatile programming is formed by a pair of complementary transistors preferably having a common drain and a common gate. The common gate is...
5404328 Memory cell having floating gate and semiconductor memory using the same  
A memory cell for storing data includes a first field effect transistor having a source receiving a first voltage, a floating gate, and a drain receiving data to be written into the memory cell and...
5357466 Flash cell with self limiting erase and constant cell current  
A Flash memory cell has a self-limiting erase to prevent over-erase and delivers a preset constant read current. The memory cell comprises first and second MOS transistors. The first and second...
5355007 Devices for non-volatile memory, systems and methods  
An electrically-erasable, electrically-programmable read-only memory cell is formed in a layer of semiconductor (1062) of a first conductivity type. A first heavily doped region (1022) and a second...
5343424 Split-gate flash EEPROM cell and array with low voltage erasure  
Each unit cell (10) of a flash EEPROM array (50) includes a control gate (38) having a section (38b) disposed in series between a program section (34a) of a floating gate (34) and a source (18) to...
5329487 Two transistor flash EPROM cell  
A two-transistor flash EPROM cell includes a first floating gate transistor for programming the cell and a second merged transistor for reading the cell. The first transistor, a floating gate...
5324972 Semiconductor non-volatile memory device and method of manufacturing the same  
According to this invention, a semiconductor non-volatile memory device includes a semiconductor substrate, insulating films formed on the semiconductor substrate and having at least two types of...
5303197 Non-volatile semiconductor memory device having EEPROM cell, dummy cell, and sense circuit for increasing reliability and enabling one-bit operation  
A non-volatile semiconductor memory device comprises an EEPROM cell, a dummy cell, and a sense circuit. The EEPROM cell, the dummy cell and the sense circuit are operatively connected to a drain...
5303187 Non-volatile semiconductor memory cell  
A non-volatile semiconductor memory cell comprises a P-type semiconductor substrate (5) and N+ diffusion regions (6) spaced apart from each other on the principal surface of a P-type substrate (5)....
5282161 Eeprom cell having a read interface isolated from the write/erase interface  
An EEPROM cell with a single level gate structure is structured over at least three distinct active areas of the semiconducting substrate over which extend portions of the single isolated gate...
5274590 Read only memory device with recharging transistor automatically supplementing current to an input node of output invertor  
A read only memory device memorizes data bits by selectively providing current paths of n-channel enhancement type memory transistors between digit lines and a ground voltage line, and one of the...
5272368 Complementary low power non-volatile reconfigurable EEcell  
A non-volatile CMOS electrically erasable programmable memory cell for configuring a PLD is disclosed. A CMOS inverter is formed by fabricating an n-channel MOSFET and a p-channel MOSFET with...
5247478 Programmable transfer-devices  
A programmable, non-volatile transfer-device includes floating gate structures to control the transfer of signals from a set of inputs to a single output. Each floating gate structure includes two...
5247477 Method of programming floating gate memory devices aided by potential applied to read channel  
Improved methods of programming floating gate memory devices such as MOS EPROMs having a gate, a floating gate, a read channel, and a write or programming channel. Potential is applied to the read...
5212541 Contactless, 5V, high speed EPROM/flash EPROM array utilizing cells programmed using source side injection  
The present invention provides a 5V only, EPROM memory cell structure that is utilizable in high speed UV-erasable or flash EPROM contactless arrays and that uses source side injection for...
5198691 BiMOS devices and BiMOS memories  
The BiMOS devices are compact 3D devices having a coupled bipolar and MOS mechanisms integrated in one single cell. The gates cover over the bipolar regions. The bipolar regions are the tubs of the...
5194925 Electrically programmable non-volatie semiconductor memory device  
A one transistor memory cell for a flash EEPROM includes: a first control gate which is disposed on a first channel region between a source region and a drain region and separated therefrom by a...
5130769 Nonvolatile memory cell  
A floating gate is utilized which has two portions. A first portion overlies the channel region formed between the source and drain. The control gate overlies this portion of the floating gate and...
5126969 Integrated circuit including non-volatile memory cell capable of temporarily holding information  
There are provided, in addition to an ordinary operation word line for controlling a non-volatile memory upon regularly writing or reading information, a testing word line, a selection transistor,...
5111430 Non-volatile memory with hot carriers transmitted to floating gate through control gate  
A non-volatile memory includes a charge injecting electrode, a control electrode, and a floating electrode. The charge injecting electrode generates hot carriers by a tunnel effect. The control...
5103425 Zener regulated programming circuit for a nonvolatile memory  
Zener diodes that are formed concurrently with flash EEPROM cells are utilized to regulate programming voltages for programming a flash EEPROM cell (37). A selected bit-line (38) is voltage...
5103273 Nonvolatile memory array having cells with two tunnelling windows  
A nonvolatile memory cell having separate regions for programming and erasing. The cells are formed in an array at a face of a semiconductor body, each cell including a source that is part of a...
5101378 Optimized electrically erasable cell for minimum read disturb and associated method of sensing  
A non-volatile memory apparatus having a plurality of memory cells, each memory cell including a floating gate tunnel device (130) having a drain (134) and a floating gate read transistor (140)...
Matches 101 - 150 out of 255 < 1 2 3 4 5 6 >