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6459615 Non-volatile memory cell array with shared erase device  
A non-volatile memory device is disclosed which includes an erase device that is shared among an array of memory cells. Each of the memory cells in the array includes a control device coupled to a...
6456529 Programmable impedance device  
A programmable impedance element ( 204 ) is implemented using integrated circuit techniques and devices. An impedance of the programmable impedance element is adjusted by appropriately configuring...
6411547 Nonvolatile memory cell and method for programming and/or verifying the same  
Nonvolatile memory device and a method of programming the same, is disclosed, wherein, for single level or multi-level programming of a cell, predetermined voltages are applied to a control gate,...
6356478 Flash based control for field programmable gate array  
A circuit for controlling a switching transistor in a reprogrammable FPGA device comprises first and second floating gate flash memory transistors. A first floating gate flash memory transistor has...
6324097 Single poly non-volatile memory structure and its fabricating method  
The present invention discloses a single poly non-volatile memory structure including a semiconductor substrate with two active areas divided by isolation regions. A control gate doped with N-type...
6317349 Non-volatile content addressable memory  
A content addressable memory (CAM) includes non-volatile CAM cells that are in an array similar to a conventional Flash memory array. In the CAM, each word line connects to control gates of Flash...
6282123 Method of fabricating, programming, and erasing a dual pocket two sided program/erase non-volatile memory cell  
A non-volatile memory cell is formed in a semiconductor substrate and includes a control gate and a floating gate formed over said semiconductor substrate. A first active region and a second active...
6229755 Wordline driving apparatus in semiconductor memory devices  
The present invention is directed to a wordline driving apparatus in semiconductor memory devices. The wordline driving apparatus comprises a CMOS distributed type sub-wordline driver for receiving...
6226201 Techniques to configure nonvolatile cells and cell arrays  
A memory cell (400) used to store data in an integrated circuit. The memory cell (400) is static, nonvolatile, and programmable. The layout of the memory cell is compact. A logic high output from...
6222759 Method of determining coupling ratios in a split-gate flash device  
A method of determining a coupling ratio of a split-gate memory cell includes initializing the cell, placing the cell in a reverse operation mode, sweeping a control gate voltage of the cell,...
6222765 Non-volatile flip-flop circuit  
A combination non-volatile latch circuit has a volatile latch circuit having a bit signal and an inverse bit signal. A first and a second non-volatile cell of the split gate floating gate type...
6222766 EEPROM memory cell and method of fabricating the same  
An object of the present invention is to realize a memory cell including a single polysilicon layer so as to simplify the fabrication process, improve the productivity and lower the fabrication...
6215700 PMOS avalanche programmed floating gate memory cell structure  
A non-volatile memory cell structure which includes a floating gate, a reverse breakdown element and a read transistor. The reverse breakdown element is at least partially formed in a first region...
6157568 Avalanche programmed floating gate memory cell structure with program element in first polysilicon layer  
A non-volatile memory cell structure which includes a floating gate, at least one injection element and a sense transistor. The injection element is at least partially formed in a first polysilicon...
6125060 Flash EEPROM device employing polysilicon sidewall spacer as an erase gate  
A Flash EEPROM cell employing a sidewall polysilicon spacer as an erase gate. The cell is programmed by source side channel hot electron injection and erased by poly-to-poly tunneling through a...
6118693 Electrically erasable non-volatile memory cell with integrated SRAM cell to reduce testing time  
In a programmable integrated circuit, by providing a static random access memory (SRAM) cell in each electrically erasable (E 2 ) non-volatile memory cell, testing time of circuits configured by...
6088261 Semiconductor storage device  
In a write operation, input data sequences "00", "01", "10", and "11" are converted into identification number groups "00", "02", "20", and "22", respectively, and the individual figures are stored...
6052311 Electrically erasable programmable read only flash memory  
An electrically erasable programmable read only flash memory having a buried floating gate structure buries the floating gate within the substrate. The source and drain regions are located beside...
6044018 Single-poly flash memory cell for embedded application and related methods  
A single-poly flash memory cell manufacturable by a standard CMOS fabrication process. A NMOS floating gate (32) is electrically connected to a PMOS floating gate (34). Both gates are fabricated in...
6038172 Memory device with dummy cell transistor  
A non-volatile semiconductor memory device including a memory cell transistor, a bit line connected to the memory cell transistor, a current controlling element connected between the bit line and a...
6034893 Non-volatile memory cell having dual avalanche injection elements  
A non-volatile memory cell includes a well region formed in a semiconductor substrate. First and second avalanche injection elements reside in the well region. A bifurcated floating-gate electrode...
6028789 Zero-power CMOS non-volatile memory cell having an avalanche injection element  
A zero-power non-volatile memory cell includes a control element, an avalanche injection element, and a CMOS inverter. A floating-gate electrode is capacitively coupled to the control element, the...
6026017 Compact nonvolatile memory  
A nonvolatile memory cell which is highly scalable includes a cell formed in a triple well. A pair of sources for a pair of cells on adjacent word lines each acts as the emitter of a lateral...
5966325 Semiconductor memory device with improved read speed  
A memory cell of a memory device is constructed such that a source diffusion layer is divided into blocks each containing 16 word lines, and such that a drain diffusion layer is not divided. Each...
5959896 Multi-state flash memory cell and method for programming single electron differences  
A flash memory cell. The cell includes a transistor with a floating gate that is formed from a number of crystals of semiconductor material. The crystals are disposed in the gate oxide of the...
5942780 Integrated circuit having, and process providing, different oxide layer thicknesses on a substrate  
An integrated circuit ("IC") having three different oxide layer thicknesses and a process for manufacturing the IC using a single oxide growth step is provided. A first region is formed on a...
5936883 Split gate type transistor memory device  
Split gate type transistor made by the steps of: forming a semiconductor substrate; forming a floating gate electrode over the semiconductor substrates the floating gate electrode having at least...
5923584 Dual poly integrated circuit interconnect  
An electrical interconnect overlying a buried contact region of a substrate is characterized by a deposition of a first polycrystalline silicon layer and the patterning and etching of same to form...
5905674 Nonvolatile memory and method of programming the same  
A nonvolatile memory cell includes a floating gate; a programming region, having a first current path to the floating gate, for programming by providing charge carriers to the floating gate through...
5905675 Biasing scheme for reducing stress and improving reliability in EEPROM cells  
Disclosed is a method for biasing dual row line EEPROM cells. The new biasing scheme improves the data retention lifetime of an EEPROM cell by reducing the potential difference between the control...
5896314 Asymmetric flash EEPROM with a pocket to focus electron injection and a manufacturing method therefor  
A memory cell having an asymmetric source and drain connection to virtual ground bit-lines. A main diffusion, adjacent the drain and displaced from the source, allows Fowler-Nordheim (FN) tunneling...
5867425 Nonvolatile memory capable of using substrate hot electron injection  
A nonvolatile memory cell which is highly scalable includes a cell formed in a triple well. A select transistor can have a source which also acts as the emitter of a lateral bipolar transistor. The...
5864501 Test pattern structure for endurance test of a flash memory device  
This invention relates to a test pattern structure comprising a test pattern structure for endurance test of a flash memory device comprising: at least three active regions formed on a...
5859796 Programming of memory cells using connected floating gate analog reference cell  
A reference cell (114) has a "floating gate" (116) that is tied to a voltage reference (118) in emulation of a programmed cell. An associated programming method is used which compares the voltage...
5852577 Electrically erasable and programmable read-only memory having a small unit for program and erase  
A full programmable and erasable non-volatile floating gate memory array uses an array of memory cells arranged in a plurality of rows and columns. Each cell is of the type with a first region, a...
5847993 Non-volatile programmable CMOS logic cell and method of operating same  
A programmable logic cell which includes a first transistor having a first conductivity type, and a second transistor having a second conductivity type, opposite the first conductivity type. The...
5838616 Gate edge aligned EEPROM transistor  
An electrically-erasable electrically-programmable read only memory (EEPROM) transistor is programmed and erased by electron tunneling and reduces gate induced drain leakage. The EEPROM transistor...
5822242 Asymmetric virtual ground p-channel flash cell with latid n-type pocket and method of fabrication therefor  
A memory cell having an asymmetric source and drain connection to virtual ground bit-lines providing an abrupt junction suitable for band-to-band hot electron generation and a gradual junction...
5789777 Non-volatile memory having multi-bit data cells with double layered floating gate structure  
The non-volatile memory has a storage cell complying with multi-bit data by means of a double layered floating gate architecture. The cell comprises: source 2 and drain 3 which are distant from...
5764096 General purpose, non-volatile reprogrammable switch  
A programmable interconnect which closely integrates an independent switching transistor with separate NVM programming and erasing elements. The programming element is an EPROM transistor and the...
5764569 Test structure and method to characterize charge gain in a non-volatile memory  
Disclosed is a method and apparatus for charge gain characterization of non-volatile memory cells. The test structure of the present invention includes an array of non-volatile memory cells similar...
5761116 V.sub.pp only scalable EEPROM memory cell having transistors with thin tunnel gate oxide  
An enhanced, scalable EEPROM memory cell is provided with a structure having a plurality of half-height tunnel oxide depletion mode transistors. The structure further has individual wordlines...
5761120 Floating gate FPGA cell with select device on drain  
The present invention provides for a novel programming operation of a programming portion of an FPGA interconnect cell. The programming portion has an EPROM transistor and a separated select...
5754471 Low power CMOS array for a PLD with program and erase using controlled avalanche injection  
A low power CMOS array cell for use in a PLD device is disclosed. The cell utilizes controlled avalanche injection at the p-n junction of a transistor in the CMOS cell for programming and erasing,...
5753952 Nonvolatile memory cell with P-N junction formed in polysilicon floating gate  
An integrated circuit memory cell (10) is formed with a P-N junction polycrystalline floating gate (13) with a lightly boron doped on the source side (13B) and a heavily arsenic or phosphorous...
5753950 Non-volatile memory having a cell applying to multi-bit data by double layered floating gate architecture and programming/erasing/reading method for the same  
An object of the present invention is to contribute to increase of storage capacity of a memory and to cope with an nonlinear parasitic resistance. The non-volatile memory have a cell applying to...
5747846 Programmable non-volatile memory cell  
A non-volatile memory cell having a structure having improved integration and simplified electrode wiring structure. The programmable non-volatile memory cell of the present invention adopts a...
5745412 Programmable nonvolatile memory and method of programming the same  
A nonvolatile memory cell includes a floating gate; a programming region, having a first current path to the floating gate, for programming by providing charge carriers to the floating gate through...
5742542 Non-volatile memory cells using only positive charge to store data  
An improved EEPROM structure is provided which has a longer data retention period. This is achieved by utilizing only positive charges to store data on the floating gate. The EEPROM structure...
5740106 Apparatus and method for nonvolatile configuration circuit  
A configuration circuit includes a plurality of configuration cells where each configuration cell has (a) a nonvolatile pull-up cell coupled to an output node and for coupling to a first power...
Matches 51 - 100 out of 256 < 1 2 3 4 5 6 >