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7391661 Column redundancy system for an integrated circuit memory  
A memory is organized with many memory subspaces (db<i>) each including their own read-out circuit (SA<i>). At least one redundant column (Blred) is provided within each subspace in...
7389465 Error detection and correction scheme for a memory device  
Data is read from a memory array. Before being stored in a data buffer, a Hamming code detection operation and a Reed-Solomon code detection operation are operated in parallel to determine if the...
7388781 Multi-bit-per-cell flash memory device with non-bijective mapping  
To store a plurality of input bits, the bits are mapped to a corresponding programmed state of one or more memory cells and the cell(s) is/are programmed to that corresponding programmed state. The...
7385850 Method of programming and verifying cells of a nonvolatile memory and relative NAND FLASH memory  
A method of programming cells in a nonvolatile memory is based upon a Global Verify operation and a Byte-by-byte Verify operation. The cells of a destination page of the nonvolatile memory are...
7382675 Semiconductor memory device  
According to an aspect of the invention, there is provided a semiconductor memory device including a first power source which generates a first power supply voltage, a second power source which...
7382655 Access time adjusting circuit and method for non-volatile memory  
An access time adjusting circuit is used in a non-volatile memory to obtain an optimized access time in operation. The circuit includes an access time detecting unit, used to detect a performance...
7379331 Nonvolatile semiconductor memory including redundant cell for replacing defective cell  
A nonvolatile semiconductor memory includes a cell array, redundancy array, erase circuit, timer, and controller. The cell array has a plurality of memory cells. The redundancy array has a...
7379330 Retargetable memory cell redundancy methods  
In a memory array having redundant columns, a scheme allows defective cells to be individually remapped to redundant cells in a redundant column. Redundant cells in one redundant column replace...
7369434 Flash memory with multi-bit read  
A memory device is described that uses extra data bits stored in a multi-level cell (MLC) to provide error information. An example embodiment provides a memory cell that uses more than 2 X logic...
7362611 Non-volatile memory copy back  
Data move operations in a memory device are described that enable identification of data errors. During a write operation, identified errors are flagged and used to provide an error status during...
7359243 Memory cell repair using fuse programming method in a flash memory device  
A method for repairing cells of a flash memory array includes using a fuse memory array circuit. The fuse memory cells are initially programmed. The locations of defective memory cells of the main...
7359242 Semiconductor memory device with small number of repair signal transmission lines  
In an embodiment, a semiconductor memory device has a small number of repair signal transmission lines. The semiconductor memory device includes m repair redundancy blocks, each including n repair...
7355909 Column redundancy reuse in memory devices  
A method for column redundancy re-use includes arranging the memory array into a plurality of addressable first array columns and a plurality of addressable second array columns. The column...
7355892 Partial page fail bit detection in flash memory devices  
A flash memory device, and a method of operating the same, is disclosed. The array of the flash memory device is arranged in pages of memory cells, each page having memory cells associated into...
7352629 Systems for continued verification in non-volatile memory write operations  
Temporary lock-out is provided while programming a group of non-volatile memory cells to more accurately program the memory cells. After successfully verifying that the threshold voltage of a...
7352622 Data arrangement and data arranging method in storage device  
The disclosure relates to a data arranging method of a flash memory for improving access performance. The method includes steps of storing a first data sector to a page of the flash memory; storing...
7352621 Method for enhanced block management  
A method and apparatus is described herein for managing bad blocks/sectors in a nonvolatile memory. Upon detecting an input/output fault to a target block in a nonvolatile memory, the target block...
7352620 Non-volatile semiconductor device and method for automatically recovering erase failure in the device  
A spare sector is in a blank state beforehand. Each time the erasing is carried out in practical use, the number of erase pulses is counted or the presence/absence of overcurrent flowing when the...
7349254 Charge-trapping memory device and methods for its manufacturing and operation  
A charge-trapping memory device includes an array of non-volatile memory cells. The array has at least a first sector and a second sector. Each sector includes a multiplicity of memory cells. Each...
7349253 Memory device and method for testing memory devices with repairable redundancy  
A memory device and method for testing memory devices with repairable redundancy is disclosed. In one embodiment, both the regular memory area and the redundant memory area are subject to the same...
7336537 Handling defective memory blocks of NAND memory devices  
Apparatus and methods are provided. A NAND memory device has a memory array comprising a plurality of memory blocks and a volatile latch coupled to each of the memory blocks for selectively...
7333364 Cell-downgrading and reference-voltage adjustment for a multi-bit-cell flash memory  
A flash memory has multi-level cells (MLC) that can each store multiple bits per cell. Blocks of cells can be downgraded to fewer bits/cell when errors occur, or for storing critical data such as...
7330370 Enhanced functionality in a two-terminal memory array  
A memory array with enhanced functionality is presented. Each cell in the array includes a pair of memory element electrodes. A read current across the pair of memory element electrodes is...
7328380 Memory scrubbing logic  
An example memory scrubbing logic is provided. The logic may be operably connectable to a main memory and a processor. The memory access logic may include a memory for mirroring a main memory...
7321959 Control method of a non-volatile memory apparatus  
A control method of a non-volatile memory apparatus, which can execute data writing normally after the next startup even when a process is interrupted because of the occurrences of abnormal...
7321513 Semiconductor device and method of generating a reference voltage therefor  
A semiconductor device includes at least one reference cell ( 6 ), a cascode circuit ( 8 ) that has at least two current mirror circuits ( 30, 33 and 30, 34 ) and outputs voltages dependent on a...
7319612 Performing multiple read operations via a single read command  
In one embodiment, the present invention includes a method for performing a plurality of read operations on a nonvolatile array of a memory according to a single read command, and storing data from...
7317636 Nonvolatile semiconductor memory, a data write-in method for the nonvolatile semiconductor memory and a memory card  
A nonvolatile semiconductor memory includes a memory cell array, a page buffer that is connected to the memory cell array and retains program verification results of a write-in operation of...
7313037 RFID system including a memory for correcting a fail cell and method for correcting a fail cell using the same  
A radio frequency identification (RFID) system and a method for correcting a failed cell using the same are provided. The RFID system effectively corrects randomly distributed cell data by using a...
7313030 Differential flash memory programming technique  
The invention relates flash memory programming techniques. An object of the invention is to provide a flash memory programming technique avoiding problems of the known state of the art and in...
7313022 Non-volatile semiconductor memory  
A non-volatile semiconductor memory device includes a memory cell array having a plurality of non-volatile memory cells, a decode circuit configured to decode address data as input thereto to...
7313019 Step voltage generation  
A step voltage generator includes multiple trainable voltage references. Each of the trimmable voltage references uses a flash cell with a variable threshold voltage and a feedback loop to trim a...
7307887 Continued verification in non-volatile memory write operations  
Temporary lock-out is provided while programming a group of non-volatile memory cells to more accurately program the memory cells. After successfully verifying that the threshold voltage of a...
7305596 Nonvolatile memory and nonvolatile memory apparatus  
To provide a technique which enables a load on a controller to be reduced by rapidly detecting n-bit errors during writing/erasing on a chip in ECC in a nonvolatile memory. A flash memory of the...
7304893 Method of partial page fail bit detection in flash memory devices  
A flash memory device, and a method of operating the same, is disclosed. The array of the flash memory device is arranged in pages of memory cells, each page having memory cells associated into...
7304891 Apparatus and method for improving write/read endurance of non-volatile memory  
An apparatus for improving write/read endurance of non-volatile memory includes a non-volatile memory area including a plurality of non-volatile memory cells to store data, and an endurance...
7295469 Nonvolatile semiconductor memory device with a ROM block settable in a write/erase inhibit mode  
A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a...
7289364 Programmable memory device with an improved redundancy structure  
An electrically programmable memory device is proposed including: a matrix of memory cells arranged in a plurality of memory arrays and at least one redundancy array; and a substituting structure...
7286400 Non-volatile semiconductor memory device with pass/fail detection circuit  
A non-volatile semiconductor memory device includes: a memory cell array, in which electrically rewritable and non-volatile memory cells are arranged: a sense amplifier circuit configured to read...
7286399 Dedicated redundancy circuits for different operations in a flash memory device  
A flash memory device can include a bank including normal memory cells and redundant memory cells arranged in a matrix of rows and columns. A read redundancy circuit is configured to generate read...
7283408 Nonvolatile memory apparatus enabling data to be replaced prior to supplying read data and prior to supplying write data  
A nonvolatile memory apparatus which need not compare an access address with a faulty address every time for rescuing from any fault is to be provided. The apparatus has memory arrays, data...
7283395 Memory device and method for operating the memory device  
A memory device comprises a memory cell array ( 1 ) with a multitude of memory cells ( 111 ). Each of the memory cells ( 111 ) is assigned to one of a multitude of blocks ( 15 ). Each memory cell (...
7277346 Method and system for hard failure repairs in the field  
A semiconductor system and method for repairing failures of a packaged integrated circuit system are provided. The method includes detecting a failure associated with a packaged integrated circuit...
7277323 Non-volatile semiconductor memory  
A non-volatile semiconductor memory is disclosed, which comprises a plurality of memory cell arrays each having a number-of-rewrites storage region allocated to a portion of a corresponding cell...
7277322 Semiconductor memory device having ECC circuit  
A semiconductor device includes a memory cell array and first and second replica bit lines. A plurality of memory cells are arranged in an array form on the memory cell array. The first replica bit...
7274611 Method and architecture to calibrate read operations in synchronous flash memory  
Architecture to calibrate read operations in non-volatile memory devices. In one embodiment, a synchronous flash memory is disclosed. The synchronous flash memory includes a read sense amplifier, a...
7272058 Nonvolatile semiconductor memory device having redundant relief technique  
A nonvolatile semiconductor memory device including associating means for associating a faulty block with a redundant block, a block switching circuit for selecting the associated redundant block...
7272049 Nonvolatile semiconductor memory device having uniform operational characteristics for memory cells  
A NAND-type nonvolatile semiconductor memory device comprising a cell string that comprises a dummy cell interposed between and connected in series to a string selection transistor and a...
7266017 Method for selective erasing and parallel programming/verifying of cell blocks in a flash EEprom system  
A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. A chunk of user data is programmed into a group of...
7266015 Redundancy substitution method, semiconductor memory device and information processing apparatus  
A redundancy substitution method for memory cells within an electrically writable and erasable semiconductor memory device, includes detecting a memory cell having a tendency of a charge loss...
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