Matches 1 - 46 out of 46
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7403417 Non-volatile semiconductor memory device and method for operating a non-volatile memory device  
Embodiments of the invention relate to non-volatile memory devices and their methods of manufacture. Embodiments comprise an array of non-volatile memory cells, the array comprising a multiplicity...
7397714 Setting method of chip initial state  
Fuse data is supplied to each of a plurality of function blocks through a transfer path using shift registers. When the reliability of fuse elements is low, there is a possibility that a part of...
7397703 Non-volatile memory with controlled program/erase  
A method for programming/erasing a non-volatile memory (NVM) includes performing a program/erase operation on a portion of the NVM using a first set of parameters. The method further includes...
7397697 Multi-bit-per-cell flash EEPROM memory with refresh  
A multibit-per-cell non-volatile memory divides the suitable threshold voltages of memory cells into ranges corresponding to allowed states for storage of data and ranges corresponding to forbidden...
7394713 Fuse memory cell with improved protection against unauthorized access  
A memory device is provided, the memory device having a memory cell, a programming unit for programming the memory cell, and a switching unit for optionally connecting or isolating a terminal of...
7394691 Semiconductor memory device which prevents destruction of data  
A plurality of memory cells each storing n values (n is a natural number which is not smaller than 3) are arranged in a matrix form in a memory cell array, and each memory cell is connected with a...
7394690 Method for column redundancy using data latches in solid-state memories  
A memory has defective locations in its user portion replaceable by redundant locations in a redundant portion. Data latches in the user and redundant portions allow data sensed from or to be...
7394689 NAND flash memory device having security redundancy block and method for repairing the same  
In one aspect, a NAND flash memory device is provided which includes a plurality of main blocks for storing main data, a security block for storing security data, and a plurality of redundancy...
7394688 Nonvolatile memory  
The memory device according to an embodiment of the invention prepares a reference field (reference value range) corresponding to each logical value and if the threshold value of the cell is within...
7391661 Column redundancy system for an integrated circuit memory  
A memory is organized with many memory subspaces (db<i>) each including their own read-out circuit (SA<i>). At least one redundant column (Blred) is provided within each subspace in...
7389465 Error detection and correction scheme for a memory device  
Data is read from a memory array. Before being stored in a data buffer, a Hamming code detection operation and a Reed-Solomon code detection operation are operated in parallel to determine if the...
7388799 Semiconductor memory device  
A semiconductor memory device for consuming a uniform amount of current includes a memory cell block including a N normal wordline and a M preliminary wordline; a refresh address counting block for...
7388782 Semiconductor integrated circuit device  
A semiconductor integrated circuit device includes a memory cell array having a plurality of blocks, a storage unit, a block replacement information register group, and a bad block flag register...
7388781 Multi-bit-per-cell flash memory device with non-bijective mapping  
To store a plurality of input bits, the bits are mapped to a corresponding programmed state of one or more memory cells and the cell(s) is/are programmed to that corresponding programmed state. The...
7385850 Method of programming and verifying cells of a nonvolatile memory and relative NAND FLASH memory  
A method of programming cells in a nonvolatile memory is based upon a Global Verify operation and a Byte-by-byte Verify operation. The cells of a destination page of the nonvolatile memory are...
7382675 Semiconductor memory device  
According to an aspect of the invention, there is provided a semiconductor memory device including a first power source which generates a first power supply voltage, a second power source which...
7382655 Access time adjusting circuit and method for non-volatile memory  
An access time adjusting circuit is used in a non-volatile memory to obtain an optimized access time in operation. The circuit includes an access time detecting unit, used to detect a performance...
7379359 Nonvolatile semiconductor memory  
A regular sense amplifier and a defect-information sense amplifier are provided for each regular sector and each defect-information sector, respectively. This can prevent an excess load from being...
7379331 Nonvolatile semiconductor memory including redundant cell for replacing defective cell  
A nonvolatile semiconductor memory includes a cell array, redundancy array, erase circuit, timer, and controller. The cell array has a plurality of memory cells. The redundancy array has a...
7379330 Retargetable memory cell redundancy methods  
In a memory array having redundant columns, a scheme allows defective cells to be individually remapped to redundant cells in a redundant column. Redundant cells in one redundant column replace...
7376012 Memory system and data writing method  
A data writing method is disclosed. In a memory system comprising a NAND flash memory and a controller which controls the memory, the memory system storing data provided from a host to the NAND...
7369434 Flash memory with multi-bit read  
A memory device is described that uses extra data bits stored in a multi-level cell (MLC) to provide error information. An example embodiment provides a memory cell that uses more than 2 X logic...
7362613 Flash EEPROM system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks  
A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features...
7362612 Program method for flash memory capable of compensating for the reduction of read margin between states  
The invention provides a programming method for a flash memory device including first and second bitlines connected with a plurality of memory cells for storing multi-bit data indicating one of a...
7362611 Non-volatile memory copy back  
Data move operations in a memory device are described that enable identification of data errors. During a write operation, identified errors are flagged and used to provide an error status during...
7359243 Memory cell repair using fuse programming method in a flash memory device  
A method for repairing cells of a flash memory array includes using a fuse memory array circuit. The fuse memory cells are initially programmed. The locations of defective memory cells of the main...
7359242 Semiconductor memory device with small number of repair signal transmission lines  
In an embodiment, a semiconductor memory device has a small number of repair signal transmission lines. The semiconductor memory device includes m repair redundancy blocks, each including n repair...
7355911 Semiconductor memory component and method for testing semiconductor memory components having a restricted memory area (partial good memories)  
A semiconductor memory component and method for testing semiconductor memory components having a restricted memory area (partial good memories is disclosed. In one embodiment, in order to test the...
7355909 Column redundancy reuse in memory devices  
A method for column redundancy re-use includes arranging the memory array into a plurality of addressable first array columns and a plurality of addressable second array columns. The column...
7355892 Partial page fail bit detection in flash memory devices  
A flash memory device, and a method of operating the same, is disclosed. The array of the flash memory device is arranged in pages of memory cells, each page having memory cells associated into...
7352629 Systems for continued verification in non-volatile memory write operations  
Temporary lock-out is provided while programming a group of non-volatile memory cells to more accurately program the memory cells. After successfully verifying that the threshold voltage of a...
7352622 Data arrangement and data arranging method in storage device  
The disclosure relates to a data arranging method of a flash memory for improving access performance. The method includes steps of storing a first data sector to a page of the flash memory; storing...
7352621 Method for enhanced block management  
A method and apparatus is described herein for managing bad blocks/sectors in a nonvolatile memory. Upon detecting an input/output fault to a target block in a nonvolatile memory, the target block...
7352620 Non-volatile semiconductor device and method for automatically recovering erase failure in the device  
A spare sector is in a blank state beforehand. Each time the erasing is carried out in practical use, the number of erase pulses is counted or the presence/absence of overcurrent flowing when the...
7349254 Charge-trapping memory device and methods for its manufacturing and operation  
A charge-trapping memory device includes an array of non-volatile memory cells. The array has at least a first sector and a second sector. Each sector includes a multiplicity of memory cells. Each...
7349253 Memory device and method for testing memory devices with repairable redundancy  
A memory device and method for testing memory devices with repairable redundancy is disclosed. In one embodiment, both the regular memory area and the redundant memory area are subject to the same...
7336537 Handling defective memory blocks of NAND memory devices  
Apparatus and methods are provided. A NAND memory device has a memory array comprising a plurality of memory blocks and a volatile latch coupled to each of the memory blocks for selectively...
7336536 Handling defective memory blocks of NAND memory devices  
Apparatus and methods are provided. A NAND memory device has a memory array comprising a plurality of memory blocks and a volatile latch coupled to each of the memory blocks for selectively...
7333364 Cell-downgrading and reference-voltage adjustment for a multi-bit-cell flash memory  
A flash memory has multi-level cells (MLC) that can each store multiple bits per cell. Blocks of cells can be downgraded to fewer bits/cell when errors occur, or for storing critical data such as...
7330370 Enhanced functionality in a two-terminal memory array  
A memory array with enhanced functionality is presented. Each cell in the array includes a pair of memory element electrodes. A read current across the pair of memory element electrodes is...
7328380 Memory scrubbing logic  
An example memory scrubbing logic is provided. The logic may be operably connectable to a main memory and a processor. The memory access logic may include a memory for mirroring a main memory...
7321959 Control method of a non-volatile memory apparatus  
A control method of a non-volatile memory apparatus, which can execute data writing normally after the next startup even when a process is interrupted because of the occurrences of abnormal...
7321513 Semiconductor device and method of generating a reference voltage therefor  
A semiconductor device includes at least one reference cell ( 6 ), a cascode circuit ( 8 ) that has at least two current mirror circuits ( 30, 33 and 30, 34 ) and outputs voltages dependent on a...
7319612 Performing multiple read operations via a single read command  
In one embodiment, the present invention includes a method for performing a plurality of read operations on a nonvolatile array of a memory according to a single read command, and storing data from...
7317636 Nonvolatile semiconductor memory, a data write-in method for the nonvolatile semiconductor memory and a memory card  
A nonvolatile semiconductor memory includes a memory cell array, a page buffer that is connected to the memory cell array and retains program verification results of a write-in operation of...
7317633 Protection of NROM devices from charge damage  
A method for protecting NROM devices from charge damage during process steps, the method including providing X-decoder structure for word line connections, wherein each word line is connected to a...
Matches 1 - 46 out of 46