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9019767 Nonvolatile memory device and operating method thereof  
A nonvolatile memory device includes a channel vertically extending from a substrate, a plurality of memory cells stacked along the channel; a source region connected to a first end portion of the...
9019774 Method and system for minimizing number of programming pulses used to program rows of non-volatile memory cells  
A flash memory device programs cells in each row in a manner that minimizes the number of programming pulses that must be applied to the cells during programming. The flash memory device includes...
9001571 6T static random access memory cell, array and memory thereof  
A 6T static random access memory cell, array, and memory thereof are provided, in which the memory cell includes a first inverter, a second inverter, a first access transistor, and a second access...
8971129 NROM device with reduced power unit  
A method includes minimizing current leaking through a virtual ground pipe during access of NROM memory cells. The minimizing includes operating two neighboring memory cells generally together,...
8964470 Method and architecture for improving defect detectability, coupling area, and flexibility of NVSRAM cells and arrays  
Several preferred embodiments of 1S1F 16T NVSRAM, 1S1F 20T NVSRAM, 1S2F 22T NVSRAM, 1S2F 14T NVSRAM cells are proposed, regardless of 1-poly, 2-poly, PMOS or NOS flash cell structures. Two...
8964485 Memory circuit with transistors having different threshold voltages and method of operating the memory circuit  
A memory circuit includes a memory cell, a data line coupled to the memory cell, a sense amplifier having an input terminal, a precharge circuit coupled to the input terminal of the sense...
8947122 Non-volatile latch structures with small area for FPGA  
A latch circuit and method includes providing a first tri-gate non-volatile device, providing a second tri-gate non-volatile device, coupling the first tri-gate non-volatile device to the second...
8942029 ***WITHDRAWN PATENT AS PER THE LATEST USPTO WITHDRAWN LIST***
Memory device
 
A memory device including first to fourth memory cell arrays and a driver circuit including a pair of bit line driver circuits and a pair of word line driver circuits is provided. The first to...
8929136 8T NVSRAM cell and cell operations  
One or more embodiments of 8T NVSRAM cell are provided for improving NVSRAM memory architecture with reduced cell size as opposed to the prior art of 12T NVSRAM cell. This novel 8T NVSRAM cell...
8885427 Precharge circuit and non-volatile memory device  
A precharge circuit includes a precharge unit configured to apply a voltage of a precharge voltage terminal to a data line during a precharge operation, and a sensing unit configured to disable...
8861271 High reliability non-volatile static random access memory devices, methods and systems  
A device can include a plurality of memory cells, each memory cell including at least one latch circuit coupled between two data nodes, a first nonvolatile section coupled to a first data node,...
8819337 Storage module and method for determining whether to back-up a previously-written lower page of data before writing an upper page of data  
A storage module and method are disclosed for determining whether to back-up a previously-written lower page of data before writing an upper page of data. In one embodiment, a storage module...
8792275 Non-volatile static random access memory (NVSRAM) device  
A non-volatile static random access memory (NVSRAM) device includes a volatile circuit and a non-volatile circuit. Under normal operations when an external power is supplied, the volatile circuit...
8724384 Multiple-bit per cell (MBC) non-volatile memory apparatus and system having polarity control and method of programming same  
A Multiple-bit per Cell (MBC) non-volatile memory apparatus, method, and system wherein a controller for writing/reading data to/from a memory array controls polarity of data by selectively...
8724382 Multiple-bit per cell (MBC) non-volatile memory apparatus and system having polarity control and method of programming same  
A Multiple-bit per Cell (MBC) non-volatile memory apparatus, method, and system wherein a controller for writing/reading data to/from a memory array controls polarity of data by selectively...
8659945 Nonvolatile memory device and method of operating same  
A nonvolatile memory device comprises a bulk region and a plurality of memory cells connected to a source line and a plurality of wordlines. The method comprises applying a source line voltage to...
8654581 Integrated circuit comprising a non-dedicated terminal for receiving an erase program high voltage  
The disclosure relates to an integrated circuit electrically powered by a supply voltage and comprising a memory electrically erasable and/or programmable by means of a second voltage greater than...
8576627 Memory array with inverted data-lines pairs  
At least one data-line pair has a first data line aligned with a first column of memory cells and a second data line aligned with a second column of memory cells. The first data line is coupled to...
8565017 Device for supplying a high erase program voltage to an integrated circuit  
The disclosure relates to a device for supplying to at least one integrated circuit a high voltage for erasing and/or programming of a memory. The device includes at least one contact terminal...
8422294 Symmetric, differential nonvolatile memory cell  
Some embodiments relate to a differential memory cell. The memory cell includes a first transistor having a source, a drain, a gate, and a body. A first capacitor has a first plate and a second...
8381075 Low-power redundancy for non-volatile memory  
A static RAM redundancy memory for use in combination with a non-volatile memory array, such as ferroelectric RAM (FRAM), in which the power consumption of the SRAM redundancy memory is reduced....
8369144 Semiconductor device and method of manufacturing the same  
According to one embodiment, a semiconductor device includes a semiconductor substrate including a device region which is isolated by a device isolation film, a first conductive layer provided on...
8363470 Memory device of the electrically erasable and programmable type, having two cells per bit  
The memory device includes a memory cell unit of the electrically erasable and programmable non-volatile type including two memory cells respectively connected to two bit lines via two bit line...
8363454 SRAM bit cell  
A semiconductor memory bit cell includes an inverter latch including a pair of cross-coupled inverters. A first transistor has a gate coupled to a first control line and a source coupled to the...
8355292 Volatile memory elements with soft error upset immunity  
Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors. To overcome...
8351261 Device for supplying a high erase program voltage to an integrated circuit  
The disclosure relates to a device for supplying to at least one integrated circuit a high voltage for erasing and/or programming of a memory. The device includes at least one contact terminal...
8351260 Integrated circuit comprising a non-dedicated terminal for receiving an erase program high voltage  
The disclosure relates to an integrated circuit electrically powered by a supply voltage and comprising a memory electrically erasable and/or programmable by means of a second voltage greater than...
8320178 Push-pull programmable logic device cell  
A memory cell includes a non-volatile p-channel transistor having a source coupled to a first potential, a drain, and a gate. A non-volatile n-channel transistor has a source coupled to a second...
8264889 Memory device and semiconductor device  
A memory device has a pair of conductive layers and an organic compound having a liquid crystal property that is interposed between the pair of conductive layers. Data is recorded in the memory...
8209460 Dual memory chip package operable to access heterogeneous memory chips  
A dual-chip package is disclosed which includes at least two memory chips each of which may contain buffer and flash memories having different address systems from each other. Each memory chip may...
8154936 Single-ended bit line based storage system  
A single-ended bit line based storage system. The storage system includes a first set of storage cells, a second set of storage cells, a first set of reference storage cells, a second set of...
8139415 Phase-change memory device  
A phase-change memory device is capable of reducing current consumption and preventing performance deterioration caused due to line load by improving a process of selecting memory cells for a...
8081510 Semiconductor integrated circuit and unstable bit detection method for the same  
A semiconductor integrated circuit including a nonvolatile memory cell is provided with a detection/word line voltage control circuit for sequentially supplying two or more mutually different...
8018768 Non-volatile static random access memory (NVSRAM) device  
A non-volatile static random access memory (NVSRAM) device includes a volatile circuit and a non-volatile circuit. Under normal operations when an external power is supplied, the volatile circuit...
7983085 Memory array with inverted data-line pairs  
At least one data-line pair has a first data line aligned with a first column of memory cells and a second data line aligned with a second column of memory cells. The first data line is coupled to...
7978515 Semiconductor storage device and electronic equipment therefor  
A semiconductor storage device includes a first memory cell for storing two kinds of states, a second memory cell for storing two kinds of states, and a sense amplifier for detecting a potential...
7969780 Nonvolatile semiconductor memory using an adjustable threshold voltage transistor in a flip-flop  
An object of this invention is to provide a rewritable nonvolatile memory cell that can have a wide reading margin, and can control both a word line and a bit line by changing the level of Vcc. As...
7952923 Multiple bit per cell non volatile memory apparatus and system having polarity control and method of programming same  
A Multiple-bit per Cell (MBC) non-volatile memory apparatus, method, and system wherein a controller for writing/reading data to/from a memory array controls polarity of data by selectively...
7920419 Isolated P-well architecture for a memory device  
A memory device and a method to prevent or reduce program disturb by isolating P-wells of strings in a non-volatile memory array. During a program operation, the isolated P-wells may be coupled to...
7916539 Differential, level-shifted EEPROM structures  
Memory embodiments are provided to operate in memory systems which are configured to have a system ground and a system substrate that are biased at different voltages. At least one of these...
7796418 Programmable memory cell  
A disclosed embodiment is a programmable memory cell comprising an elevated ground node having a voltage greater than a common ground node by an amount substantially equal to a voltage drop across...
7791940 Integrated circuit with switching unit for memory cell coupling, and method for producing an integrated circuit for memory cell coupling  
An integrated circuit has a plurality of first memory cells, which are electrically coupled along a first line, and additionally has a plurality of second memory cells which are electrically...
7787312 Semiconductor device and controlling method for the same  
A semiconductor device has a plurality of bit lines BL provided in a memory cell area 101, a plurality of word lines WL provided crossing the plurality of bit lines BL, a plurality of diffusion...
7778076 Memory unit  
A memory unit is provided herein. Two non-volatile devices are used to store a logic state of the memory unit into the non-volatile devices. Although a power supply for the memory unit is shut...
7760540 Combination SRAM and NVSRAM semiconductor memory array  
A semiconductor memory array having a first memory cell array with a number of first memory cells and a second cell array with a number of second memory cells. The memory cells in the first and...
7750671 Nonvolatile programmable logic circuit  
A nonvolatile programmable logic circuit using a ferroelectric memory performs a nonvolatile memory function and an operation function without additional memory devices, thereby reducing power...
7729166 Multiple-bit per cell (MBC) non-volatile memory apparatus and system having polarity control and method of programming same  
A Multiple-bit per Cell (MBC) non-volatile memory apparatus, method, and system wherein a controller for writing/reading data to/from a memory array controls polarity of data by selectively...
7719908 Memory having read disturb test mode  
Embodiments of the invention relate to the testing and reduction of read disturb failures in a memory, e.g., an array of SRAM cells. A read disturb test mode may be added during wafer sort to...
7692964 Source-biased SRAM cell with reduced memory cell leakage  
A Static Random Access Memory (SRAM) cell having a source-biasing mechanism for leakage reduction. In standby mode, the cell's wordline is deselected and a source-biasing potential is provided to...
7663917 Non-volatile static memory cell  
A static memory cell comprising a pair of cross-coupled inverters (10, 12) which is “shadowed” with non-volatile memory elements (14, 16) so that data written in the static memory can be stored in...
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