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7586157 Non-volatile memory with dual voltage select gate structure  
A select gate structure for a non-volatile storage system include a select gate and a coupling electrode which are independently drivable. The coupling electrode is adjacent to a word line in a...
7580279 Flash memory cells with reduced distances between cell elements  
An anti-reflective coating (ARC) is formed over the various layers involved in a cell fabrication process. The ARC is selectively etched such that the edges of the etched areas of the ARC slope...
7508714 Memory array incorporating mirrored NAND strings and non-shared global bit lines within a block  
An exemplary NAND string memory array includes at least one plane of memory cells, said memory cells comprising thin film modifiable conductance switch devices and which cells are arranged in a...
7426129 Layout structures in semiconductor memory devices including bit line layout for higher density migration  
A true bit line can extend across a memory cell area of the memory device in a first direction and a complementary bit line can extend across the memory cell area in a second direction opposing the...
7400534 NAND flash memory and data programming method thereof  
A semiconductor integrated circuit device includes even-numbered bit lines, odd-numbered bit lines, cell source lines, first memory elements electrically connected between the even-numbered bit...
7301820 Non-volatile memory dynamic operations  
A dynamic programming method for a non-volatile storage device is described. Memory cells are provided arrayed in R rows. Sub bit lines are provided coupled to voltage supply lines through select...
7245546 Reduced area, reduced programming voltage CMOS efuse-based scannable non-volatile memory bitcell  
An integrated circuit chip includes a number of memory bitcells. Each bitcell includes: a latch having a sense node; a programming transistor having an efficient saturation region of operation; and...
7139194 Nonvolatile semiconductor memory  
Each nonvolatile memory cell transistor has such directivities that a current flows only from the drain to the source and that charge is exchangeable only at the source. The source of one of a pair...
7088618 Method of evaluating characteristics of semiconductor memory element, and method of extracting model parameter of semiconductor memory element  
A characteristic evaluating method of precisely obtaining a resistance value of an offset region in a semiconductor memory element constructed so that the resistance value of the offset region...
6952033 Semiconductor memory array of floating gate memory cells with buried bit-line and raised source line  
A self aligned method of forming an array of floating gate memory cells, and an array formed thereby, wherein each memory cell includes a trench formed into a surface of a semiconductor substrate,...
6844588 Non-volatile memory  
A semiconductor device includes a non-volatile memory, such as an electrically erasable programmable read only memory (EEPROM) array of memory cells. The memory is arranged as an array of cells in...
6813186 Nonvolatile semiconductor memory device  
A nonvolatile semiconductor memory device of the present invention includes: a plurality of memory blocks each including a memory array including a plurality of memory cells, a plurality of word...
6788573 Non-volatile semiconductor memory and method of operating the same  
The present invention discloses a non-volatile semiconductor memory device and a method of operating the same. More specifically, the present invention includes a semiconductor substrate having...
6646914 Flash memory array architecture having staggered metal lines  
A memory array includes a plurality of sets of transistors, each set including a pair of transistors in series. Each such pair of transistors is connected between a pair of adjacent bit lines. Each...
6621733 Segmented bit line EEPROM page architecture  
An EEPROM segment bit line page memory array includes a plurality of bit lines extending in a Y-direction; a plurality of word lines extending in an X-direction; a plurality of sub-bit lines...
6611457 Read-only nonvolatile memory  
A read-only nonvolatile memory in which the leakage current of unselected memory cell transistors is suppressed. Adjacent memory cell transistors are commonly connected to drain lines, and adjacent...
6574140 Low voltage single supply CMOS electrically erasable read-only memory  
P channel EEPROM cells are designed for integration into arrays written with single polarity signals developed from small, low power charge pumps. These cells reduce the additional masking steps...
6529406 Semiconductor device with power supply wirings and expanded wirable regions for users  
A plurality of basic unit blocks include a memory cell array and first data lines transmitting data read out from memory cell arrays. Second data lines are arranged in an upper layer in a plurality...
6516256 Apparatus for storing data in a motor vehicle  
An apparatus for storing data of a device, in particular of a motor vehicle, which is to be monitored, in which apparatus the data are preferably stored by means of a control unit in a memory unit....
6469929 Structure and method for high speed sensing of memory arrays  
A method for sensing the state of a memory cell includes both dynamic and static clamping of the bit line coupled to a memory cell. This dual clamping configuration/operation ensures a quick charge...
RE37311 Parallel type nonvolatile semiconductor memory device and method of using the same  
On a semiconductor substrate of a first conductive type is formed a well layer of the same conductive type as that of the substrate in electrically separated that is, physically separated and...
6201732 Low voltage single CMOS electrically erasable read-only memory  
P channel EEPROM cells are designed for integration into arrays written with single polarity signals developed from small, low power charge pumps. These cells reduce the additional masking steps...
6046938 Structure of a flash memory  
A structure of a flash memory is disclosed. The flash memory includes a common drain, a memory unit which has at least one memory cell, and a depletion mode selector transistor. The depletion mode...
5940320 Voltage compensating output driver circuit  
An output driver circuit that compensates for variations in supply voltage to provide more consistent switching speed characteristics. In one embodiment, the output driver circuit includes a...
5894437 Concurrent read/write architecture for a flash memory  
A semiconductor device having an array of flash memory cells and for each column of cells, a global read bit line, a global write bit line, and a plurality of local bit lines, wherein the column of...
5892713 Nonvolatile semiconductor memory device  
The memory mat is divided in two banks, which share the sense & latch circuit. As an example of the circuit operation, the information contained in the memory cells in a block of four bit lines...
5875128 Semiconductor memory  
In a semiconductor memory including NOR type cells in which memory cell transistors are located between adjacent bit lines and virtual ground lines, the connection pattern of bit line selecting...
5875127 Non-volatile semiconductor memory device having a floating gate storage capacitor and method of operating thereof  
A memory array circuit has a matrix of column lines and row lines. A plurality of non-volatile storage capacitors, each having a floating gate for the storage of charges, are arranged in the...
5847998 Non-volatile memory array that enables simultaneous read and write operations  
A non-volatile memory having a non-volatile memory array arranged as a plurality of sectors each containing an array of non-volatile memory cells. The non-volatile memory includes independent read...
5793678 Parellel type nonvolatile semiconductor memory device method of using the same  
On a semiconductor substrate of a first conductive type is formed a well layer of the same conductive type as that of the substrate in electrically separated that is, physically separated and...
5793666 Single-chip memory system having an array of read-only memory cells  
To make a memory system highly integrated, a memory system includes a memory cell array including a first unit block and a second unit block having a plurality of read-only memory (ROM) cells, a...
5748538 OR-plane memory cell array for flash memory with bit-based write capability, and methods for programming and erasing the memory cell array  
A memory cell array of a flash electrically erasable programmable read only memory (EEPROM) includes a plurality of transistor cells arranged in rows and columns. The sources of transistor cells in...
5740108 Series-structured read-only memory having word lines arranged independently for each row of a memory cell array  
A semiconductor memory device which has a reduced current consumption. A memory block includes a pair of memory cell columns each of which includes a plurality of memory cells connected in series,...
5717636 EEPROM memory with contactless memory cells  
In a flash-EEPROM array, the cells in each row are grouped into pairs connected to the same diffused source line and to two different diffused bit lines, and the adjacent pairs of cells are spaced...
5691938 Non-volatile memory cell and array architecture  
An improved contactless EPROM array, EPROM cell design, and method for fabricating the same is based on a unique drain-source-drain configuration, in which a single source diffusion is shared by...
5654916 Semiconductor memory device having an improved sense amplifier arrangement  
A semiconductor memory device in which a plurality of data lines of a memory array comprising storage transistors arranged in a matrix form as those having a high or low threshold voltage according...
5640345 Semiconductor memory device and fabrication process  
Provided between a control gate electrode and a channel region of the EEPROM memory cell is a capacitor. Formed on the channel region are a first gate dielectric layer of silicon oxide, a first...
5623442 Memory cells and memory devices with a storage capacitor of parasitic capacitance and information storing method using the same  
An object of the present invention is to provide a DRAM of a special form, a non-volatile memory cell incorporating the DRAM, and a semiconductor device which incorporates a DRAM structure and a...
5615151 Semiconductor integrated circuit operable and programmable at multiple voltage levels  
Any one of the internal circuits of a semiconductor integrated circuit is made to operate both at a relatively high operating voltage having a predetermined allowable range and at a relatively low...
5610858 Non-volatile semiconductor memory device and method of manufacturing the same  
Memory cells, each formed of an EEPROM, are series-connected with transistors. Blocks, each of which is constructed by one memory cell and one transistor connected in series, are arranged in a...
5583808 EPROM array segmented for high performance and method for controlling same  
An EPROM memory array and method of controlling the array. The array is divided into array segments, with each segment having alternating bit and source lines. Each segment includes several rows of...
5574685 Self-aligned buried channel/junction stacked gate flash memory cell  
An improved one-transistor flash EEPROM cell structure and a method for making the same is provided so that the effective channel length dimension is independent of the critical dimensions of the...
5568421 Semiconductor memory device on which selective transistors are connected to a plurality of respective memory cell units  
A semiconductor memory device of this invention includes a semiconductor substrate, a plurality of memory cell units each having a plurality of memory cells each of which has a charge storage layer...
5557124 Flash EEPROM and EPROM arrays with select transistors within the bit line pitch  
Flash EEPROM array and EPROM arrays are described. The EEPROM array has EEPROM areas with arrays of EEPROM transistors, at least one control area per EEPROM area and columns of a first polysilicon...
5555521 Method of operating the semiconductor memory storing analog data and analog data storing apparatus  
The operational method is disclosed, for storing analog data in an electrically programmable and erasable memory cell. The memory cell includes a transistor having a source, a drain, a control gate...
5550722 Electric lamp  
An electric lamp including a light source, a lamp cap having a shell and a base, a housing connected to the light source and to the lamp cap, and a ballast which is electrically connected to the...
5550772 Memory array utilizing multi-state memory cells  
A non-volatile memory system is disclosed which includes an array of multi-state N channel floating gate memory cells along with associated control circuitry for programming, reading and erasing...
5544099 Method of writing data into electrically erasable and programmable read only memory cell without disturbance to other cells  
A floating gate type field effect transistor increases the threshold during an application of a write-in pulse to the control gate electrode thereof so as to inject hot electrons into the floating...
5526322 Low-power memory device with accelerated sense amplifiers  
An AND array for an erasable programmable logic device (EPLD) includes word-line transition detectors for indicating high-to-low word-line transitions. Such transitions are a condition precedent...
5524097 Power saving sense amplifier that mimics non-toggling bitline states  
A sense amplifier of the present invention provides power savings of between 30% to 70% for typical usage of a programmable logic device. In one embodiment, this sense amplifier includes circuitry...
Matches 1 - 50 out of 167 1 2 3 4 >