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7391645 Non-volatile memory and method with compensation for source line bias errors  
Source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the source of a memory cell is erroneously biased by a voltage drop...
7388792 Memory management device and memory device  
A memory management device for managing a nonvolatile semiconductor memory which comprises a plurality of blocks, and permits data to be erased in units of one block, the memory management device...
7388780 Semiconductor memory device and control method for the semiconductor memory device  
A memory cell array for memorizing data with any of 0th through fourth threshold voltages and a flag memory unit for memorizing a flag data showing a chronological sequence relationship between...
7388779 Multiple level programming in a non-volatile device  
The programming method of the present invention minimizes program disturb by initially programming cells on the same wordline with the logical state having the highest threshold voltage. The...
7385848 Semiconductor storage device and electronic equipment  
A semiconductor storage device has a memory cell array composed of a plurality of arrayed memory cells, word lines, bit lines, a bit line charging and discharging circuit, and a readout section....
7382663 Erase voltage generator circuit for providing uniform erase execution time and nonvolatile memory device having the same  
An erase voltage generation circuit providing a uniform erase execution time and a non-volatile semiconductor memory device having the same, in which the erase voltage generation circuit includes a...
7382660 Method for accessing a multilevel nonvolatile memory device of the flash NAND type  
Multi-level programming allows for writing a first and a second bit in selected cells by separately programming the first bit from the second bit. Programming of the first bit determines a shifting...
7379340 Sense amplifier circuit in non-volatile semiconductor memory comprising a boosting capacitor for boosting the potential at sense node  
A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to...
7379338 Method and system for regulating a program voltage value during multilevel memory device programming  
Regulating a program voltage value during multilevel memory device programming includes utilizing a program path duplicate in an output pump regulator circuit. Further, the output pump regulator...
7376016 Method of writing to non-volatile semiconductor memory device storing information depending on variation in level of threshold voltage  
In a flash memory, after an initial write operation ends, each bit line associated with a memory cell subjected to a write is precharged and each bit line associated with a memory cell that is not...
7376009 Semiconductor memory device which stores plural data in a cell  
A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n...
7372732 Pulse width converged method to control voltage threshold (Vt) distribution of a memory cell  
A method of operating on a plurality of non-volatile multi-level memory cells is disclosed. The memory cells have at least a first, second, third and fourth program level. Each of program levels...
7372730 Method of reading NAND memory to compensate for coupling between storage elements  
A method for reading a non-volatile memory arranged in columns and rows which reduces adjacent cell coupling, sometimes referred to as the Yupin effect. The method includes the steps of: selecting...
7369441 Sensing circuit for multi-level flash memory  
A sensing circuit for multi-level flash memory is disclosed. The advantages of the sensing circuit are reducing the circuit size, reducing the testing time for tuning reference voltage and...
7369434 Flash memory with multi-bit read  
A memory device is described that uses extra data bits stored in a multi-level cell (MLC) to provide error information. An example embodiment provides a memory cell that uses more than 2 X logic...
7366033 3-level non-volatile semiconductor memory device and method of driving the same  
A page buffer for a non-volatile semiconductor memory device includes a switch configured to couple a first bitline coupled to a first memory cell to a second bitline coupled to a second memory...
7366022 Apparatus for programming of multi-state non-volatile memory using smart verify  
In a non-volatile memory, the initiation of program verification is adaptively set so that programming time is decreased. In one approach, non-volatile storage elements are programmed based on a...
7366014 Double page programming system and method  
A method for programming an electrically programmable memory including a plurality of memory cells arranged in individually-selectable memory cell sets each including at least one memory cell. The...
7363556 Testing apparatus and testing method  
A testing apparatus for testing a memory-under-test includes a writing section for writing preset test data into each page of said memory-under-test to test said memory-under-test and a fail memory...
7362617 Nonvolatile semiconductor memory device and method of rewriting data thereof  
The nonvolatile semiconductor memory device of the present invention includes a memory cell array wherein data is stored in a nonvolatile state based on a difference in memory information between...
7359246 Memory device with a ramp-like voltage biasing structure based on a current generator  
A memory device includes a plurality of memory cells each one for storing a value, at least one reference cell, biasing means for biasing a set of selected memory cells and the at least one...
7359240 Flash memory device with multi level cell and burst access method therein  
A flash memory device including memory cells, each memory cell configured to store bits, a sensing circuit configured to sequentially sense, for each memory cell, sets of the bits of the memory...
7355891 Fabricating bi-directional nonvolatile memory cells  
A memory transistor having a pair of separate floating gates overlying end regions of a channel and a control gate that overlies the floating gates and a central region of the channel effectively...
7355876 Memory array circuit with two-bit memory cells  
A high-speed nonvolatile memory array has two-bit memory cells, each connected to a mutually adjacent pair of sub-bit lines. The sub-bit lines are connected to a common power supply line through...
7352627 Method, system, and circuit for operating a non-volatile memory array  
As part of the present invention, a memory cell may be operated using reference cells having a threshold offset circuit. According to some embodiments of the present invention, a threshold offset...
7352619 Electronic memory with binary storage elements  
An electronic memory using true and complementary dual bit lines and dual binary storage elements cell architecture comprising a memory cell pair with four binary storage elements with each memory...
7352618 Multi-level cell memory device and associated read method  
A NOR flash memory device comprises a memory cell adapted to store at least two bits of data. A read operation is performed on the memory cell by generating a reference current with a first...
7345921 Method and system for a programming approach for a nonvolatile electronic device  
Aspects for programming a nonvolatile electronic device include performing an initial verify step of a programming algorithm with an initial type of reference voltage value, and performing one or...
7345914 Use of flash memory blocks outside of the main flash memory array  
A method, device, and system are disclosed. In one embodiment, the device comprises an array of flash memory blocks to store information in a multiple bit per cell mode, one or more flash memory...
7345913 Semiconductor memory device  
A semiconductor memory device, comprising: a memory cell array of a plurality of memory cell units, each memory cell unit including a plurality of serially connected memory cells formed on the same...
7342829 Memory device and method for operating a memory device  
A memory device ( 1 ) includes a memory array ( 2 ). The memory array ( 2 ) has at least one memory area ( 5 ) that includes a plurality of conductive lines ( 3 ) and a plurality of memory cells (...
7342827 Charge trap-type 3-level non-volatile semiconductor memory device and method of driving the same  
Disclosed herein is a charge trap-type 3-level non-volatile semiconductor memory device and method of driving the same. The charge trap-type 3-level non-volatile semiconductor memory device...
7342821 Hot-carrier-based nonvolatile memory utilizing differing transistor structures  
A memory circuit includes a latch having a first node and a second node, a first MIS transistor operable to couple between the first node and a predetermined node, a second MIS transistor operable...
7336538 Page buffer circuit and method for multi-level NAND programmable memories  
A page buffer for an electrically programmable memory including at least one read/program unit having a coupling line operatively associable with at least one of said bit lines and adapted to at...
7336532 Method for reading NAND memory device and memory cell array thereof  
A method for reading a NAND flash memory device having plural normal cells, which utilizes plural reference bit lines associated with plural reference cells to read the normal cells in one phase to...
RE40110 Nonvolatile semiconductor memory device for storing multivalued data  
A multivalued memory has data of state “0”, state “1”, state “2”, and state “3” whose threshold voltages increase in that order. In a first-page write operation, a memory cell whose...
7330376 Method for memory data storage by partition into narrower threshold voltage distribution regions  
A method for data storage of a memory unit and a memory unit using the same are provided in the present invention. The method for data storage of a memory unit includes: first, dividing a memory...
7330373 Program time adjustment as function of program voltage for improved programming speed in memory system  
In a non-volatile memory system, the programming time period allocated for the program pulse is adjusted as a function of the voltage level of the pump pulse required so that the total number of...
7330370 Enhanced functionality in a two-terminal memory array  
A memory array with enhanced functionality is presented. Each cell in the array includes a pair of memory element electrodes. A read current across the pair of memory element electrodes is...
7327609 Methods of program-verifying a multi-bit nonvolatile memory device and circuit thereof  
Methods of verifying a program state may be provided for a non-volatile memory device including a multi-bit memory cell transistor providing more than two different program states. More...
7327602 Methods of accelerated life testing of programmable resistance memory elements  
A method of testing a programmable resistance memory element. The method includes applying a plurality of reset pulses to the memory element. Each of the reset pulses having an energy which is...
7324375 Multi-bits storage memory  
A nonvolatile memory apparatus including a control circuit, plural terminals having clock, command and other terminals, data and command registers, and plural nonvolatile memory cells. The clock...
7324374 Memory with a core-based virtual ground and dynamic reference sensing scheme  
A core-based multi-bit memory ( 400 ) having a dual-bit dynamic referencing architecture ( 408, 410 ) fabricated on the memory core ( 401 ). A first reference array ( 408 ) and a second reference...
7321509 Compensating for coupling in non-volatile storage  
Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge...
7317639 Two-bit charge trap nonvolatile memory device and methods of operating and fabricating the same  
Two-bit programmable nonvolatile memory devices and methods of operating and fabricating the same are provided. The device comprises a plurality of device isolation layers, a plurality of word...
7315477 Compensating for coupling during read operations of non-volatile memory  
Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge...
7315055 Silicon-oxide-nitride-oxide-silicon (SONOS) memory devices having recessed channels  
Unit cells of silicon-oxide-nitride-oxide-silicon (SONOS) memory devices are provided. The unit cells include an integrated circuit substrate and a SONOS memory cell on the integrated circuit...
7313019 Step voltage generation  
A step voltage generator includes multiple trainable voltage references. Each of the trimmable voltage references uses a flash cell with a variable threshold voltage and a feedback loop to trim a...
7310255 Non-volatile memory with improved program-verify operations  
In programming a non-volatile memory involving alternately applying a programming pulse and verifying the programming, time is saved in the program verify portion when, depending on the states of...
7308525 Method of managing a multi-bit cell flash memory with improved reliablility and performance  
A method of storing data by providing a flash memory device including a plurality of memory cells; each of the memory cells is capable of storing data bits. First data bits are stored into memory...
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