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7391659 Method for multiple step programming a memory cell  
A memory cell is programmed by injecting charge into a charge storage layer of the memory cell. A desired programmed charge results in the charge storage layer over an edge portion of a channel...
7385846 Reduction of adjacent floating gate data pattern sensitivity  
The method for programming non-volatile memory cells erases the memory cells to be programmed. The memory cells are then programmed to a reduced floating gate voltage that takes into account...
7372743 Controlling a nonvolatile storage device  
A control method for a nonvolatile storage device having a storage mode in which in a memory cell provided with a trapping dielectric layer 1-bit data is stored depending on the presence or absence...
7372730 Method of reading NAND memory to compensate for coupling between storage elements  
A method for reading a non-volatile memory arranged in columns and rows which reduces adjacent cell coupling, sometimes referred to as the Yupin effect. The method includes the steps of: selecting...
7369434 Flash memory with multi-bit read  
A memory device is described that uses extra data bits stored in a multi-level cell (MLC) to provide error information. An example embodiment provides a memory cell that uses more than 2 X logic...
7362615 Methods for active boosting to minimize capacitive coupling effect between adjacent gates of flash memory devices  
A NAND flash memory device incorporates a unique booster plate design. The booster plate is biased during read and program operations and the coupling to the floating gates in many cases reduces...
7362610 Programming method for non-volatile memory and non-volatile memory-based programmable logic device  
A method for programming a flash memory cell comprises providing input data to the flash cell and providing a segmented programming pulse to the flash memory cell. The segmented programming pulse...
7359239 Non-volatile memory device having uniform programming speed  
Flash memory devices having a cell string structure. According to the present invention, the size of a first group of memory cells connected to a first word line and a second group of memory cells...
7355887 Non-volatile semiconductor memory device having non-selected word lines adjacent to selected word lines being charged at different timing for program disturb control  
A non-volatile semiconductor memory device comprises a memory cell array of data-rewritable non-volatile memory cells or memory cell units containing the memory cells, and a plurality of word lines...
7352618 Multi-level cell memory device and associated read method  
A NOR flash memory device comprises a memory cell adapted to store at least two bits of data. A read operation is performed on the memory cell by generating a reference current with a first...
7339821 Dual-gate nonvolatile memory and method of program inhibition  
A memory circuit and a method is provided for programming a dual-gate memory cell without program disturb in other dual-gate memory cells in the memory circuit coupled by common word lines. In one...
7333362 Electrically erasable and programmable, non-volatile semiconductor memory device having a single layer of gate material, and corresponding memory plane  
The semiconductor memory device includes an electrically erasable programmable non-volatile memory cell having a single layer of gate material and including a floating-gate transistor and a control...
7324377 Apparatus and method for programming and erasing virtual ground EEPROM without disturbing adjacent cells  
A method is described for erasing a selected data region in an NROM cell that is a member of a virtual ground NROM EEPROM array. The method provides that erasing the selected data region does not...
7319621 Reducing DQ pin capacitance in a memory device  
A system and method to operate an electronic device, such as a memory chip, with a data driver circuit that is configured to reduce data pin (DQ) capacitance. In a driver circuit that is comprised...
7319617 Small sector floating gate flash memory  
To control the problem of program and erase disturb in flash memory arrays having multiple sectors of cells grouped in each isolation wells of the flash memory array, a refresh procedure is used...
7319609 Non-volatile memory device with a programming current control scheme  
A non-volatile memory device includes at least one current source coupled to a bit line, along which at least two memory cells sharing a common source line are connected, for generating a...
7313018 Methods and apparatus for a non-volatile memory device with reduced program disturb  
A non-volatile memory device includes a plurality of power control circuits interfaced via a single Y multiplexer with an array of memory cells. The multiple power control circuits provide multiple...
7301805 Pipelined programming of non-volatile memories using early data  
The present invention presents techniques whereby a memory system interrupts a programming process and restarts it including additional data. More specifically, when a memory system programs data...
7298647 Operating techniques for reducing program and read disturbs of a non-volatile memory  
The present invention presents a non-volatile memory having a plurality of erase units or blocks, where each block is divided into a plurality of parts sharing the same word lines to save on the...
7295466 Use of recovery transistors during write operations to prevent disturbance of unselected cells  
A memory array and method for performing a write operation in a memory array that eliminates parasitic coupling between selected and unselected bitlines and protects memory cells on unselected...
7287118 Maintaining an average erase count in a non-volatile storage system  
Methods and apparatus for maintaining an average erase count in a system memory of a non-volatile memory system are disclosed. According to one aspect of the present invention, a method for...
7283398 Method for minimizing false detection of states in flash memory devices  
The present invention provides a method for determining program and erase states in flash memory devices. Specifically, one embodiment of the present invention discloses a method for minimizing...
7283391 Semiconductor memory device  
A semiconductor memory device comprises: a plurality of memory elements; at least one bit line, wherein a memory operation is performed via at least a portion of the bit line with respect to at...
7280395 Methods for neutralizing holes in tunnel oxides of floating-gate memory cells and devices  
Methods for neutralizing holes in tunnel oxides of floating-gate memory cells and devices using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a...
7274614 Flash cell fuse circuit and method of fusing a flash cell  
A flash cell fuse circuit includes a fuse cell array, a plurality of switch circuits and a plurality of fuse sense amplifiers. The fuse cell array outputs first signals in response to word line...
7272039 Minimizing adjacent wordline disturb in a memory device  
A selected wordline that is coupled to cells for programming is biased with a programming voltage. The unselected wordlines that are adjacent to the selected wordline are biased at a first...
7259986 Circuits and methods for providing low voltage, high performance register files  
Circuits and methods are provided to implement low voltage, higher performance semiconductor memory devices such as CMOS static random access memory (SRAM) or multi-port register files. For...
7224613 Operating techniques for reducing effects of coupling between storage elements of a non-volatile memory operated in multiple data states  
A non-volatile memory system having an array of memory cells with at least one storage element each is operated with a plurality of storage level ranges per storage element. A flash electrically...
7221008 Bitline direction shielding to avoid cross coupling between adjacent cells for NAND flash memory  
A NAND flash memory structure and method of making a flash memory structure with shielding in the bitline direction as well as in wordline and diagonal directions from Yupin effect errors and from...
7218554 Method of refreshing charge-trapping non-volatile memory using band-to-band tunneling hot hole (BTBTHH) injection  
A method of using a non-volatile memory that utilizes a charge-trapping layer for data storage is described. A refresh step is performed, after the non-volatile memory is subject to multiple...
7215575 Detecting over programmed memory  
In a non-volatile semiconductor memory system (or other type of memory system), a memory cell is programmed by changing the threshold voltage of that memory cell. Because of variations in the...
7215573 Method and apparatus for reducing operation disturbance  
A memory array has a plurality of memory cells, arranged in a plurality of rows and columns. Each cell has at least four terminals. The array has a plurality of column lines with each column line...
7206235 Apparatus for controlled programming of non-volatile memory exhibiting bit line coupling  
The effects of bit line-to-bit line coupling in a non-volatile memory are addressed. An inhibit voltage is applied on a bit line of a storage element to be programmed to inhibit programming during...
7184307 Flash memory device capable of preventing program disturbance according to partial programming  
A non-volatile semiconductor memory device disclosed herein includes arrays of memory cells arranged along rows and columns. The columns are divided into at least two column regions and each row is...
7180774 Semiconductor integrated circuit device including first, second and third gates  
A semiconductor integrated device having a plurality of memory cells, each including a floating gate, a control gate and an auxiliary gate formed over a side surface of the floating gate through an...
7177183 Multiple twin cell non-volatile memory array and logic block structure and method therefor  
Extremely dense memory cell structures provide for new array structures useful for implementing memory and logic functions. An exemplary non-volatile memory array includes a first plurality of...
7164606 Reverse fowler-nordheim tunneling programming for non-volatile memory cell  
In accordance with a method of programming an NVM array that includes 4-transistor PMOS non-volatile memory (NVM) cells having commonly connected floating gates, for all the cell's in the array...
7158408 Current source control in RFID memory  
These systems and techniques relating to RFID tags include current source control in RFID memory. According to an aspect, a radio frequency identification tag includes an antenna, a radio frequency...
7145799 Chip protection register unlocking  
An improved Flash memory device is described with a protection register lock bit erase enable circuit. A bond pad coupled to the lock bit erase enable circuit of the improved Flash memory is not...
7142455 Positive gate stress during erase to improve retention in multi-level, non-volatile flash memory  
A new method for improving the accuracy of read-write operations in a multi-level flash memory cell is disclosed. The method reduces the read margin disturbance caused by the accumulation of holes...
7142454 System and method for Y-decoding in a flash memory device  
A system and method for column selection in a non-volatile memory cell array is disclosed. A group of memory cells is arranged in a rectangular array having rows (X-dimension) and columns...
7120051 Pipelined programming of non-volatile memories using early data  
The present invention presents techniques whereby a memory system interrupts a programming process and restarts it including additional data. More specifically, when a memory system programs data...
7118961 Stitch and select implementation in twin MONOS array  
In this invention, by offering specific array-end structures and their fabrication method, the three resistive layers of diffusion bit line, control gate and word gate polysilicons, where control...
7113431 Quad bit using hot-hole erase for CBD control  
The present invention pertains to a technique for erasing bits in a dual bit memory in a manner that maintains complementary bit disturb control of bit-pairs of memory cells wherein each bit of the...
7102924 Techniques of recovering data from memory cells affected by field coupling with adjacent memory cells  
Techniques of overcoming a degradation of the apparent charge levels stored in one row of memory cells as a result of subsequently programming an adjacent row of memory cells. After storing the...
7099204 Current sensing circuit with a current-compensated drain voltage regulation  
The present invention facilitates more accurate data reads by compensating for parasitic behavior—thus regulating the voltage at the drain of a core memory cell rather than at the output of a...
7099195 Methods for neutralizing holes in tunnel oxides of floating-gate memory cells and devices  
Methods for neutralizing holes in tunnel oxides of floating-gate memory cells and devices using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a...
7085168 Programming method for controlling memory threshold voltage distribution  
A method for programming one or more memory cells is disclosed. The one or more memory cells need to be two sides operated. After verifying both sides of each memory cell to identify the sides of...
7085161 Non-volatile semiconductor memory with large erase blocks storing cycle counts  
In a flash EEPROM system that is divided into separately erasable blocks of memory cells with multiple pages of user data being stored in each block, a count of the number of erase cycles that each...
7085157 Nonvolatile memory device and semiconductor device  
A method for speeding up data writing and reducing power consumption by reducing the variation of the threshold voltage of each of non-volatile memory cells at data writing. When writing data in a...
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