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5663903 Flat-cell read-only memory  
The memory cells of a read-only memory are connected in parallel between adjacent bus-bit lines. The selection of tile sub-bit lines is through a selector logic decoder. The decoder has many rows...
5663922 Method for the anticipated reading of serial access memory, and memory pertaining thereto  
A method and apparatus for reading a memory, such that the address decoding is started when the address bits have not yet all been received. All the information elements corresponding to the...
5652450 Nonvolatile semiconductor storage device  
According to the present invention, a nonvolatile semiconductor storage device for applying to each word line either one of a selected voltage and a non-selected voltage, corresponding to a...
5646901 CMOS memory cell with tunneling during program and erase through the NMOS and PMOS transistors and a pass gate separating the NMOS and PMOS transistors  
An apparatus and method, the apparatus including an NMOS pass gate separating NMOS and PMOS transistors of a CMOS memory cell configured for tunneling during program and erase through the NMOS and...
5640345 Semiconductor memory device and fabrication process  
Provided between a control gate electrode and a channel region of the EEPROM memory cell is a capacitor. Formed on the channel region are a first gate dielectric layer of silicon oxide, a first...
5483483 Read-only memory device  
A semiconductor memory device includes a current driving transistor composed of a bipolar transistor which is coupled to a corresponding bit line for increasing the bit line current. The collector...
5469384 Decoding scheme for reliable multi bit hot electron programming  
A nonvolatile memory circuit having a decoding scheme for reliable multiple bit hot electron programming. The nonvolatile memory circuit has a memory array in which data received at each data input...
5463587 Nonvolatile semiconductor system  
It is an object of the present invention to optimize the range of threshold voltage in a flash EEPROM and to simplify the verifying operation. In memory transistors (1)-(4) and a dummy memory...
5450341 Non-volatile semiconductor memory device having memory cells, each for at least three different data writable thereinto selectively and a method of using the same  
A method of writing or reading at least three different data in each memory cell, in a non-volatile semiconductor memory device having a plurality of memory cells, each memory cell having floating...
5450363 Gray coding for a multilevel cell memory system  
A memory system contains a plurality of memory cells, a sensing circuit, and a translator circuit. The memory cells store one of a plurality of threshold levels, wherein the threshold levels...
5450354 Non-volatile semiconductor memory device detachable deterioration of memory cells  
A non-volatile semiconductor memory device capable of electrical programming including a plurality of memory cells, means for selecting at least one memory cell from the plurality of memory cells,...
5434815 Stress reduction for non-volatile memory cell  
Non-volatile semiconductor core memory performance is enhanced by reduced stress on core memory cells. Stress is reduced by selectable application of bias voltages to the sense line under control...
5428572 Program element for use in redundancy technique for semiconductor memory device  
Improvement of a fuse for use in the redundancy technique particularly for a semiconductor memory device. The fuse is constituted by an MIS type transistor having a gate insulating layer, which...
5424978 Non-volatile semiconductor memory cell capable of storing more than two different data and method of using the same  
A non-volatile semiconductor memory device capable of selectively storing one of at least three different data comprises a memory array including a plurality of memory cells, each having a control...
5424992 Method and device for detecting and controlling an array source signal discharge for a memory erase operation  
An array source signal discharge controller device (10) includes a pulse converter circuit (12) that receives an erase pulse signal (ERPULSE). The pulse converter circuit (12) converts the erase...
5418743 Method of writing into non-volatile semiconductor memory  
A method of using a non-volatile semiconductor memory comprising a plurality of row and column lines, a plurality of memory cells disposed at intersections of the row and column lines and a...
5412601 Non-volatile semiconductor memory device capable of storing multi-value data in each memory cell  
An electrically erasable non-volatile semiconductor memory device comprising a plurality of row lines and column lines, a plurality of memory cells connected in a matrix to the plurality of row...
5394359 MOS integrated circuit with adjustable threshold voltage  
The MOS cell with adjustable threshold voltage is a cell of the type with a memory that is electrically-erasable and programmable by storage of charges by tunnel effect in a floating gate. To...
5369608 Apparatus for relieving standby current fail of memory device  
An apparatus for relieving the standby current fail of a memory device which completely relieves a memory device by suppressing the increasing standby current consumption when the standby current...
5363329 Semiconductor memory device for use in an electrically alterable read-only memory  
This disclosure relates to an electrically alterable memory device which can be switched from a high resistance state to a low resistance state. The device increases the concentration of...
5359554 Semiconductor memory device having an energy gap for high speed operation  
A semiconductor device is provided comprising a nonvolatile memory cell through which an LSI and a higher operating speed are achieved. A drain region, an insulating layer partly overlaying the...
5349221 Semiconductor memory device and method of reading out information for the same  
In a memory cell according to the present invention, when positive high voltages are respectively applied to a gate( 20 ) and a drain region( 14 ) and a source region( 13 ) is grounded, hot...
5349222 Single gate MOS type nonvolatile memory and operating method thereof  
The present invention provides nonvolatile semiconductor memory which has advantages permitting the cell of the memory circuit to integrate, the memory circuit to be easy to manufacture, and the...
5345416 High density nonvolatile memory and decoder of the same  
A non-volatile memory comprises memory cells M arranged in a matrix (MB), word lines (W1 to Wn) for row selection, sub-bit lines (B: B12, B21, B22, B31), sub-column lines (C: C11, C12, C22), a...
5343423 FET memory device  
A plurality of trap-type memory transistors are formed in separate wells of a semiconductor substrate, and arranged to constitute a memory matrix. Each well contains the memory transistors...
5341010 Semiconductor device including nonvolatile memories  
The present invention can provide the memory circuit which has advantages in integration and the manufacturing expense and is easy to manufacture. The nonvolatile memory 21 comprises a P type well...
5313419 Self-aligned trench isolation scheme for select transistors in an alternate metal virtual ground (AMG) EPROM array  
The present invention provides a self-aligned trench isolation scheme for the MOS select transistors in an alternate metal virtual ground (AMG) EPROM array architecture. The new isolation scheme...
5311049 Non-volatile semiconductor memory with outer drain diffusion layer  
A non-volatile semiconductor memory wherein in a semiconductor substrate at both sides of a gate structure, a source diffusion layer and drain diffusion layer having an opposite conductivity type...
5291048 Non-volatile storage device with impurities in nitride toward source side  
A non-volatile storage device such as an EPROM (erasable programmable read only memory) and a method of manufacturing the same. A silicon oxide film, a silicon nitride film and a silicon oxide film...
5278440 Semiconductor memory device with improved tunneling characteristics  
A semiconductor memory is disclosed. The cell has MNOS structure, and comprises a p-type silicon substrate 27 with n type layers 21, 23, a silicon dioxide film 19 thereon, a reduced pressure SiN...
5270980 Sector erasable flash EEPROM  
A memory device is provided that includes a plurality of floating gate memory cells arranged in an array, where each memory cell includes a control gate, a drain and a source. A decoder is provided...
5262987 Floating gate semiconductor nonvolatile memory having impurity doped regions for low voltage operation  
A semiconductor nonvolatile memory has a base semiconductor region of one conductivity type. A first semiconductor region of the one conductivity type is formed in a surface portion of the base...
5251172 Semiconductor memory apparatus having reduced amount of bit line amplification delay  
In a DRAM formed of MOS FETs, respectively different values of substrate bias voltage are applied to transistors of different types of circuit in accordance with the circuit functions, to thereby...
5241498 Non-volatile semiconductor memory device  
There is a provided non-volatile semiconductor memory device including a memory cell including a source, a drain, a floating gate, and a control gate. To read out data from the memory cell, a...
5172338 Multi-state EEprom read and write circuits and techniques  
Improvements in the circuits and techniques for read, write and erase of EEprom memory enable non-volatile multi-state memory to operate with enhanced performance over an extended period of time....
5172198 MOS type semiconductor device  
A MOS type semiconductor device includes two adjacent MOSFETs. The FETs are respectively formed on element forming areas of a P-type substrate. Each of the transistors has N + type layers serving...
5162880 Nonvolatile memory cell having gate insulation film with carrier traps therein  
A nonvolatile memory cell comprises a semiconductor substrate of first conduction type, a high-concentration impurity region of second conduction type formed on the semiconductor substrate and...
5117389 Flat-cell read-only-memory integrated circuit  
A flat-cell ROM array reduces the number of block select transistors utilized, allows for the layout of straight metal lines, while sharing the metal lines between even and odd banks, and achieves...
5097444 Tunnel EEPROM with overerase protection  
The present invention provides protection against the effects of overerasure while essentially maintaining a single transistor per memory cell through the use of an additional transistor for each...
5068696 Programmable interconnect or cell using silicided MOS transistors  
A programmable device (10) is formed from a silicided MOS transistor. The transistor (10) is formed at a face of a semiconductor layer (12), and includes a diffused drain region (17, 22) and a...
5065362 Non-volatile RAM with integrated compact static RAM load configuration  
A non-volatile random access memory (NVRAM) cell of condensed size employs a pair of programmable threshold voltage devices, e.g. MNOS (metal nitride oxide semiconductor), SNOS (silicon nitride...
5057885 Memory cell system with first and second gates  
A memory element manufactured by a thin film forming technique is disclosed. The memory element includes a gate electrode, a gate insulating film, a semiconductor layer, a source electrode, and a...
5022000 Semiconductor memory device  
A writing high voltage of one polarity or an erasing high voltage of another polarity is selectively fed, in accordance with a writing or erasing operation mode, via a switch MOSFET to the word...
5020030 Nonvolatile SNOS memory cell with induced capacitor  
A silicon substrate with a drain area formed therein is used for the base of the device. A first polysilicon gate is disposed above the substrate with a layer of gate oxide therebetween. Adjacent...
5017978 EPROM having a reduced number of contacts  
An integrated circuit includes a memory having cells arranged in rows and columns, each cell having transistor being connected between two bit lines and having a current channel, a control gate and...
5012448 Sense amplifier for a ROM having a multilevel memory cell  
A multilevel sense circuit includes a memory MOSFET having one of at least two different current carrying states and a pair of reference MOSFETs one of which has one of the two current carrying...
4998223 Programmable semiconductor memory apparatus  
A programmable semiconductor memory apparatus comprises a memory cell array, a data sense circuit for reading data from the memory cell array, and a bus line connected to a common node of a...
4964079 Electrically programmable memory with several information bits per cell  
The disclosure concerns electrically programmable memories and, notably, the memories known as EPROMs, EEPROMs, FLASH-EEPROMs. To increase the information storage capacity of a memory, it is...
4962481 EEPROM device with plurality of memory strings made of floating gate transistors connected in series  
An electrically erasable programmable semiconductor memory array for high density including a plurality of column lines; a plurality of reference lines perpendicular to the column lines; a...
4962322 Nonvolatible capacitor random access memory  
The disclosure relates to a MOSFET-protected nonvolatile capacitor cell which has a storage gate and a nonvolatile stack thereunder, the cell having a heavily doped n+ ring surrounding the storage...
Matches 51 - 100 out of 320 < 1 2 3 4 5 6 7 >