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7626850 Systems and devices for implementing sub-threshold memory devices  
Various systems and methods for implementing memory devices are disclosed. For example, some embodiments of the present invention provide sub-threshold memory devices that include a differential...
7613030 Semiconductor memory device and method for operating the same  
A semiconductor memory device is provided, which comprises an analog switch, a first inverter, a second inverter, and a clocked inverter. A first terminal of the analog switch is electrically...
7598544 Hybrid carbon nanotude FET(CNFET)-FET static RAM (SRAM) and method of making same  
Hybrid carbon nanotube FET (CNFET), static ram (SRAM) and method of making same. A static ram memory cell has two cross-coupled semiconductor-type field effect transistors (FETs) and two nanotube...
7542333 Logic cell protected against random events  
A memory cell stores information in the form of a first logic level and a second logic level that are complementary to each other. The memory cell includes a first storage circuit and a second...
7539931 Storage element for mitigating soft errors in logic  
In a preferred embodiment, the invention provides a method for reducing soft errors in logic. After obtaining two delayed clock signals, the delayed clock signals, the clock signal, and an output...
7451384 Error recovery in asynchronous combinational logic circuits  
A system and method for providing error recovery to an asynchronous logic circuit is presented. The asynchronous logic circuit with error recovery may use temporal redundancy to compare the results...
7382667 Active termination circuit and method for controlling the impedance of external integrated circuit terminals  
An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor...
7359229 Semiconductor memory device and method of operating same  
There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory...
7106638 Active termination circuit and method for controlling the impedance of external integrated circuit terminals  
An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor...
7085156 Semiconductor memory device and method of operating same  
There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory...
7085153 Semiconductor memory cell, array, architecture and device, and method of operating same  
There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory cell and technique of reading data from and writing data into that...
6944042 Multiple bit memory cells and methods for reading non-volatile data  
Memory cells are disclosed comprising volatile and non-volatile portions, where the non-volatile portions provide storage of multiple non-volatile data states or bits per memory cell. Methods are...
6714436 Write operation for capacitorless RAM  
A method for writing data to single-transistor capacitorless (1T/0C) RAM cell, wherein the cell structure is predicated on an SOI MOS transistor that has a floating body region ( 12 ). Data is...
6643167 Semiconductor memory  
A semiconductor memory having a memory cell structure capable of reducing soft error without complicating a circuit configuration. Specifically, an inverter (I 1 ) consists of a NMOS transistor (N...
6614078 Highly latchup-immune CMOS I/O structures  
CMOS I/O structures are described which are latchup-immune by inserting p+ and n+ diffusion guard-rings into the NMOS and PMOS source side of a semiconductor substrate, respectively. P+ diffusion...
6560142 Capacitorless DRAM gain cell  
A nondestructive read, two-device gain cell for a DRAM memory, based on conventional complementary metal oxide technology is disclosed. The charge is stored on the gate of a first MOSFET, with a...
6522581 Semiconductor storage device  
A semiconductor storage device includes: a plurality of first memory arrays each including a plurality of semiconductor storage elements, in which data from an external device is written, and from...
6442062 Load-less four-transistor memory cell with different gate insulation thicknesses for N-channel drive transistors and P-channel access transistors  
A memory cell has a pair of n-ch drive MOS transistors, a pair of p-ch access MOS transistors. The access MOS transistor supply electric charge to storage nodes of the drive MOS transistors without...
6420221 Method of manufacturing a highly latchup-immune CMOS I/O structure  
CMOS I/O structures are described which are latchup-immune by inserting p+ and n+ diffusion guard-rings into the NMOS and PMOS source side of a semiconductor substrate, respectively. P+ diffusion...
6288962 Semiconductor device allowing fast signal transfer and system employing the same  
A pair of dummy signal lines transmitting dummy signals, complementary to and synchronized with a normal signal, are arranged to form a set together with a normal transfer line transmitting the...
6278287 Isolated well transistor structure for mitigation of single event upsets  
CMOS circuits are made resistant to erroneous signals produced by the impact of high energy charged particles (commonly known in the literature as Single Event Upset or SEU) by the addition of...
6252797 Masked ROM and manufacturing process therefor  
A masked ROM of a flat cell structure has a plurality of bit-line diffusion layers formed in parallel in one direction in a semiconductor. substrate, a plurality of word lines formed on the...
6208554 Single event upset (SEU) hardened static random access memory cell  
A single event upset hardened memory cell to be utilized in static random access memories is disclosed. The single event upset hardened memory cell includes a first set of cross-coupled...
6201761 Field effect transistor with controlled body bias  
A field effect transistor (FET) is formed on a silicon on insulator (SOI) substrate in the thin silicon layer above the insulating buried oxide layer. A clock signal defines a clock period with an...
6018475 MOS memory point  
The present invention relates to the use of a conventional MOS transistor as a memory point in which, during programming, the well of the MOS transistor is connected to a reference potential, the...
5850360 High-voltage N-channel MOS transistor and associated manufacturing process  
A CMOS device and process are disclosed in which two types of N-channel MOS transistors are provided, one being formed in a P-well and one being formed outside the P-well where the relatively low...
5831897 SRAM memory cell design having complementary dual pass gates  
A memory cell in which data is written and read from a pass gate. The memory cell has a connection to a first pass gate, connecting the memory cell to a bit line. Additionally, the memory cell has...
5784311 Two-device memory cell on SOI for merged logic and memory applications  
A two-MOSFET device memory cell, based on conventional SOI complementary metal oxide technology, in which charge is stored on the body of a first MOSFET, with a second MOSFET connected to the body...
5691944 Non-volatile semiconductor memory device  
In a non-volatile semiconductor memory device having a writing power source voltage which is supplied thereto exceeding a withstand voltage of a field effect transistor, the object of the present...
5668755 Semiconductor memory device having well region  
A semiconductor memory device is obtained having a triple well structure improved by preventing latch up or the like. In this semiconductor memory device, a substrate potential is applied to a p...
5570313 Memory insensitive to disturbances  
The invention concerns a memory cell insensitive to disturbances. The memory cell, that contains information in the form of two complementary logical levels (X, C(X)), each logical level being...
5546338 Fast voltage equilibration of differential data lines  
A method and a circuit for fast equilibration of complementary data lines in memory circuit following a write cycle. The circuit of the present invention separately controls the on/off timing of...
5523966 Memory cell and a memory device having reduced soft error  
Disclosed is a static type memory cell with high immunity from alpha ray-induced soft errors. The memory cell has a coupling capacitance C c between two data storage nodes 1 and 2. The p-well (or...
5517038 Semiconductor device including three-dimensionally disposed logic elements for improving degree of integration  
Adjacent memory cells has a two-layer structure formed of first layer and second layer. The first layer is provided with driver transistors of the memory cell, access transistors of the memory...
5453951 Fast voltage equilibration of complementary data lines following write cycle in memory circuits  
A method and a circuit for fast equilibration of complementary data lines in memory circuit following a write cycle. The circuit of the present invention separately controls the on/off timing of...
5446689 Semiconductor memory having a polycrystalline silicon load resistor and CMOS peripheral circuitry  
A semiconductor memory device is provided which has a plurality of memory cells each including a pair of cross-coupled metal insulated gate field effect transistors having channels of...
5420818 Static read only memory (ROM)  
A static read-only-memory (ROM) is derived from a gate array in which both P-channel transistor (24) and an N-channel transistor (30) are used to convey a logic 1 or 0 to a bitline (Bitline0). The...
5406513 Mechanism for preventing radiation induced latch-up in CMOS integrated circuits  
A CMOS circuit formed in a semiconductor substrate having improved immunity to radiation induced latch-up and improved immunity to a single event upset. The circuit architecture of the present...
5404328 Memory cell having floating gate and semiconductor memory using the same  
A memory cell for storing data includes a first field effect transistor having a source receiving a first voltage, a floating gate, and a drain receiving data to be written into the memory cell and...
5382807 Field effect thin film transistor and static-type semiconductor memory device provided with memory cell having complementary field effect transistor and method of manufacturing the same  
A structure of a thin film transistor capable of reducing the power consumption in the waiting state and stabilizing the data holding characteristic in application of the thin film transistor as a...
5375083 Semiconductor integrated circuit including a substrate having a memory cell array surrounded by a well structure  
An object of the present invention is to provide a semiconductor integrated circuit in which an EEPROM is incorporated in a highly integrated microcomputer having a twin well structure. A twin well...
5373476 Highly integrated semiconductor memory device with triple well structure  
A highly integrated semiconductor memory device, such as a DRAM, is provided with a unique triple-well structure which results in reduced junction capacitance of transistors and a smaller body...
5373468 Semiconductor memory device  
A semiconductor memory device comprises a memory cell array including a plurality of adjacently disposed first and second memory cell pairs, with bit lines defined in the memory cell array....
5363328 Highly stable asymmetric SRAM cell  
An asymmetric static random access memory cell (50 and 53) includes polysilicon load elements (55 and 56), N-channel pull-down transistors (57 and 58), and N-channel coupling transistors (59 and...
5357461 Output unit incorporated in semiconductor integrated circuit for preventing semiconductor substrate from fluctuating in voltage level  
An output circuit is incorporated in an integrated circuit for communicating with an external device, and includes a plurality of output inverting circuits. Each such inverting circuit is...
5235215 Memory device for use in power control circuits  
A memory circuit which includes a memory SCR and an output SCR is provided. The memory SCR is coupled between the input terminal and the common terminal of the memory circuit wherein the input...
5216632 Memory arrangement with a read-out circuit for a static memory cell  
A memory arrangement that includes a static memory cell with two MOSFETs that are connected such that an input signal for setting the memory cell is applied to one MOSFET, and the output of the...
5200921 Semiconductor integrated circuit including P-channel MOS transistors having different threshold voltages  
A semiconductor integrated circuit includes a first P-channel MOS transistor and a second P-channel MOS transistor. The drain of the first P-channel MOS transistor is connected to the gate of the...
5134581 Highly stable semiconductor memory with a small memory cell area  
In order to obtain a highly stable SRAM cell having a small cell area, a cell ratio R is set to be R=(W DEFF /L DEFF )/(W TEFF /L TEFF )<3 where L DEFF and W DEFF denote an effective channel...
5132930 CMOS dynamic memory device having multiple flip-flop circuits selectively coupled to form sense amplifiers specific to neighboring data bit lines  
In a metal-oxide semiconductor (MOS) dynamic formed on a semiconductor substrate, data nodes of a first flip-flop are connected to a first pair of folded bit lines. Its power supply node is...
Matches 1 - 50 out of 133 1 2 3 >