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7633819 |
Determining history state of data in data retaining device based on state of partially depleted silicon-on-insulator
A system, method and program product for determining a history state of data in a data retaining device are disclosed. A state of a partially-depleted silicon-on-insulator (PD SOI) device coupled...
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7630235 |
Memory cells, memory devices and integrated circuits incorporating the same
A memory cell is provided which includes an access transistor and a gated lateral thyristor (GLT) device. The access transistor includes a source node. The gated lateral thyristor (GLT) device...
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7613026 |
Apparatus and methods for optically-coupled memory systems
Optically-coupled memory systems are disclosed. In one embodiment, a system memory includes a carrier substrate, and a controller attached to the carrier substrate and operable to transmit and...
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7606082 |
Semiconductor circuit, inverter circuit, semiconductor apparatus, and manufacturing method thereof
The semiconductor circuit includes a voltage-controlled semiconductor device (N)N, the resistance value of which is controllable with a high voltage, the drain terminal of the N can be connected to...
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7598544 |
Hybrid carbon nanotude FET(CNFET)-FET static RAM (SRAM) and method of making same
Hybrid carbon nanotube FET (CNFET), static ram (SRAM) and method of making same. A static ram memory cell has two cross-coupled semiconductor-type field effect transistors (FETs) and two nanotube...
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7589995 |
One-transistor memory cell with bias gate
One-transistor (1T) capacitor-less DRAM cells each include a MOS transistor having a bias gate layer that separates a floating body region from a base substrate. The MOS transistor functions as a...
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7577025 |
Semiconductor memory device comprising floating body memory cells and related methods of operation
A semiconductor device comprising floating body memory cells performs read and write operations by selectively connecting bit lines and inverted bit lines to sense bit lines and inverted sense bit...
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7564709 |
Method and system for utilizing DRAM components in a system-on-chip
A system-on-chip semiconductor circuit includes a logic circuit having at least one first transistor with a thin gate dielectric, at least one dynamic random access memory cell coupled with the...
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7556869 |
Electronic device and wiring with a current induced cooling effect, and an electronic device capable of converting a temperature difference into voltage
Localized temperature increases inside integrated circuits due to heating at operation are prevented or controlled by electronic devices or wirings with CPP (current-perpendicular-to-plane)...
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7542333 |
Logic cell protected against random events
A memory cell stores information in the form of a first logic level and a second logic level that are complementary to each other. The memory cell includes a first storage circuit and a second...
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7539931 |
Storage element for mitigating soft errors in logic
In a preferred embodiment, the invention provides a method for reducing soft errors in logic. After obtaining two delayed clock signals, the delayed clock signals, the clock signal, and an output...
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7529125 |
Semiconductor device and operating method thereof
An object is to provide a semiconductor device capable of reducing an area of the semiconductor device, reading data reliably, and simplifying replacement of data. A memory cell and a data line are...
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7525832 |
Memory device and semiconductor integrated circuit
First electrode layer includes a plurality of first electrode lines (W 1 , W 2 ) extending parallel to each other. State-variable layer lying on the first electrode layer includes a plurality of...
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7518174 |
Memory cell and method for forming the same
A semiconductor memory cell structure having 4F 2 dimensions and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed in the...
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7463546 |
Method for using a passive element memory array incorporating reversible polarity word line and bit line decoders
Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for...
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7460395 |
Thyristor-based semiconductor memory and memory array with data refresh
A new memory cell can contain only a single thyristor. There is no need to include an access transistor in the cell. In one embodiment, the thyristor is a thin capacitively coupled thyristor. The...
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7443741 |
DQS strobe centering (data eye training) method
A method for calibrating a data valid window including the steps of: (A) setting a base delay of one or more datapaths to a predetermined value, (B) determining an optimum offset delay value for...
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7414883 |
Programming a normally single phase chalcogenide material for use as a memory or FPLA
A memory may be implemented with a stable chalcogenide glass which is defined as a generally amorphous chalcogenide material that does not change to a generally crystalline phase when exposed to...
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7405963 |
Dynamic data restore in thyristor-based memory device
A dynamically-operating restoration circuit is used to apply a voltage or current restore pulse signal to thyristor-based memory cells and therein restore data in the cell using the internal...
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7405967 |
Microelectronic programmable device and methods of forming and programming the same
A microelectronic programmable structure and methods of forming and programming the structure are disclosed. The programmable structure generally include an ion conductor and a plurality of...
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7382650 |
Method and apparatus for sector erase operation in a flash memory array
A memory device is provided which includes a substrate, a common P-well isolated from the substrate, a plurality of sectors, and a common sector selection transistor configured to select one of the...
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7379315 |
Apparatus and methods for optically-coupled memory systems
Optically-coupled memory systems are disclosed. In one embodiment, a system memory includes a carrier substrate, and a controller attached to the carrier substrate and operable to transmit and...
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7359238 |
Semiconductor nonvolatile storage circuit
A semiconductor nonvolatile storage circuit capable of stably storing and holding information by preventing pseudo-writing in storing/holding FETs is realized. The semiconductor nonvolatile circuit...
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7336524 |
Atomic probes and media for high density data storage
A device in accordance with embodiments of the present invention comprises a contact probe for high density data storage reading, writing, erasing, or rewriting. In one embodiment, the contact...
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7324373 |
Semiconductor device and short circuit detecting method
A short circuit detection region includes an insulating film, plural first conductor traces and plural second conductor traces which are embedded in the insulating film with only their surfaces...
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7310266 |
Semiconductor device having memory cells implemented with bipolar-transistor-antifuses operating in a first and second mode
A DAC having a memory mat including a plurality of first memory cells, and a plurality of output lines connected to the plurality of first memory cells. Each of the plurality of memory cells has a...
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7304364 |
Embossed mask lithography
Disclosed are layered groupings and methods for constructing digital circuitry, such as memory known as Permanent Inexpensive Rugged Memory (PIRM) cross point arrays which can be produced on...
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7288782 |
Use of Ta-capped metal line to improve formation of memory element films
Disclosed are methods for deposition of improved memory element films for semiconductor devices. The methods involve providing a hard mask over an upper surface of a metal line of a semiconductor...
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7242060 |
Semiconductor memory device including an SOI substrate
A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor...
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7233512 |
Content addressable memory circuit with improved memory cell stability
A Content Addressable Memory (CAM) circuit includes memory cells preferably formed as two memory cells each having internal nodes. A compare circuit is operative with the memory cells. A common...
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7203084 |
Three-dimensional memory device with ECC circuitry
The preferred embodiments described herein provide a memory device and methods for use therewith. In one preferred embodiment, a method is presented for using a file system to dynamically respond...
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7199444 |
Memory device, programmable resistance memory cell and memory array
A method of metal doping a chalcogenide material includes forming a metal over a substrate. A chalcogenide material is formed on the metal. Irradiating is conducted through the chalcogenide...
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7170779 |
Non-volatile memory using organic bistable device
The present invention provides an organic bistable device for use in non-volatile memories. The organic bistable device comprises a first and a second metal electrode sandwiching a first and a...
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7164597 |
Computer systems
A two-transistor SRAM cell includes a first FET. The first FET is an ultrathin FET of a first polarity type and includes a control electrode, a first load electrode and a second electrode. The...
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7149109 |
Single transistor vertical memory gain cell
A high density vertical single transistor gain cell is realized for DRAM operation. The gain cell includes a vertical transistor having a source region, a drain region, and a floating body region...
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7145811 |
Semiconductor storage device
A semiconductor storage device according to one embodiment of the present invention, comprising: FBCs (Floating Body Cells) which store data by accumulating a majority carrier in a floating channel...
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7142450 |
Programmable sub-surface aggregating metallization structure and method of making same
A programmable sub-surface aggregating metallization structure (“PSAM”) includes an ion conductor such as a chalcogenide-glass which includes metal ions and at least two electrodes disposed at...
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7138684 |
Semiconductor memory device including an SOI substrate
A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor...
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7131033 |
Substrate configurable JTAG ID scheme
A circuit generally comprising a core circuit and a test access port circuit. The core circuit may be configurable among a plurality of functions in response to a signal. The test access port...
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7126200 |
Integrated circuits with contemporaneously formed array electrodes and logic interconnects
The invention relates to interconnects for an integrated circuit memory device. Embodiments of the invention include processes to fabricate interconnects for memory devices in relatively few steps....
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7113423 |
Method of forming a negative differential resistance device
A negative differential resistance (NDR) field-effect transistor element is disclosed, formed on a silicon-based substrate using conventional MOS manufacturing operations. Methods for improving a...
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7110281 |
Memory cells utilizing metal-to-metal capacitors to reduce susceptibility to single event upsets
Structures and methods of adding metal-to-metal capacitors to static memory cells to reduce susceptibility to SEUs. The addition of metal-to-metal capacitors is particularly suited to programmable...
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7085156 |
Semiconductor memory device and method of operating same
There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory...
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7075820 |
Semiconductor memory device for dynamically storing data with channel body of transistor used as storage node
A semiconductor memory device includes a plurality of MIS transistors arranged at intersections of first word lines and bit lines formed on an SOI substrate and each configuring a memory cell. Each...
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7075821 |
Apparatus and method for a one-phase write to a one-transistor memory cell array
A method and apparatus for a one-phase write to a one-transistor memory cell array. In one embodiment, the method includes a one-phase write to a selected wordline of a memory cell array. Once the...
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7072205 |
Floating-body DRAM with two-phase write
A row of floating-body single transistor memory cells is written to in two phases.
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7061042 |
Double-cell memory device
A memory array device has a plurality of gate structure lines, adjacently disposed over a substrate along a direction, wherein at least a portion of the gate structure lines have memory function. A...
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7050323 |
Ferroelectric memory
A nonvolatile memory cell in the form of an SRAM is composed of ferroelectric capacitors and transistors for amplification. The memory cell comprises a first capacitor (FC 1 ) connected between a...
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7050320 |
MEMS probe based memory
Briefly, in accordance with one embodiment of the invention, a memory device may include a memory layer and a MEMS layer. The memory layer may include an integrated circuit with a multiplexer and...
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7038943 |
Memory array having 2T memory cells
The present invention relates to a memory array having a plurality of memory cells. In order to combine the compactness of DRAM with the speed and uncomplicated processing profits of SRAM the...
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