Matches 201 - 250 out of 396 < 1 2 3 4 5 6 7 8 >
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5122986 Two transistor dram cell  
A semiconductor memory cell includes a write row line, a read row line, a write column line, a read column line, a single MOS write transistor, and a single MOS read transistor. The write...
5121357 Static random access split-emitter memory cell selection arrangement using bit line precharge  
This invention relates generally to the static, random access, semiconductor memory arrays which incorporate split-emitter memory cells. The latter are accessed during a read cycle of a selected...
5117390 Semiconductor memory system for use in logic LSI's  
A semiconductor memory system includes a memory section formed on a semiconductor substrate and having decode means for decoding an address signal, and a logic section formed on the semiconductor...
5084838 Large-scale integrated circuit device such as a wafer scale memory having improved arrangements for bypassing, redundancy, and unit integrated circuit interconnection  
A plurality of unit integrated circuits mounted on a large-scale integrated circuit device, for example, a wafer scale memory, are each provided with a bypass circuit which selectively shorts input...
5077688 Semiconductor memory device having improved memory cells provided with cylindrical type capacitors  
A semiconductor memory device having a storage region constituted with the arrangement of a plurality of memory cells on a main surface of a semiconductor substrate. Each memory cell includes a...
5077687 Gallium arsenide addressable memory cell  
An addressable memory cell (10) which is composed of an interrupt transistor (20) of the field-effect type whose source (S) is connected to the input terminal (I) of the cell (10) and whose gate...
5036490 Memory device with dual cantilever means  
The memory device comprises a recording member in which perturbations are selectively formed, a probe for detecting the presence or absence of the perturbations, a first cantilever having the...
5020027 Memory cell with active write load  
A memory cell responsive to a write enable signal for storing write signals present on a pair of write bit lines and responsive to a read enable signal for presenting stored data on a pair of read...
4991136 Semiconductor associative memory device with memory refresh during match and read operations  
A semiconductor associative memory device comprises a content addressable memory cell connected to a word line, a bit line, an inversion bit line and a match line. The memory cell comprises first...
4970685 Semiconductor memory device having a divided bit line structure  
A semiconductor memory device includes an array of memory cells arranged in rows and columns, a plurality of divided bit line pairs connecting the memory cells, the divided bit line pairs extending...
4970689 Charge amplifying trench memory cell  
A gain memory cell circuit includes a storage capacitor connected between a storage node and ground, a write word line, a read word line, a second capacitor capactively coupling the read word line...
4958320 Radiation resistant bipolar memory  
A bipolar memory of a construction having high immunity to soft error attributable to alpha rays is provided. The transistors of a flip flop, i.e., the essential circuitry of the memory cell, are...
4945515 Memory writing apparatus  
An input section comprising a needle which has a fine tip portion. A data is written in a memory by applying electrical stimulation between the tip portion of the needle and the memory. A memory...
4943740 Ultra fast logic  
The logic has an extremely high speed, very low number of components and large common mode rejection, and is intended to eliminate the emitter-coupled logic (ECL). The supply voltage and power...
4942555 Bi-MOS semiconductor memory having high soft error immunity  
A semiconductor memory is provided having high reliability, and which particularly prevents data destruction by rays, and the like. In a semiconductor memory for detecting memory data from the...
4933899 Bi-CMOS semiconductor memory cell  
A Bi-CMOS ECL semiconductor memory cell having a read word line, a write word line and a read bit line is disclosed. The cell includes a bistable circuit having complimentary outputs and also...
4930104 Content-addressed memory  
A content-addressed memory which has a priority ranking circuit and/or a write control circuit provided in an output section thereof, the priority ranking circuit being adapted to be selectively...
4926378 Bipolar static RAM having two wiring lines for each word line  
There is implemented memory cells and corresponding signal lines associated therewith in bipolar type static random access memories employing wirings of multi-layer construction for transmitting a...
4922411 Memory cell circuit with supplemental current  
A memory cell circuit with a pair of load bipolar transistors and a pair of control bipolar transistors, and with a pair of supplemental transistors providing current shunts.
4888628 Dynamic memory in integrated circuit form  
In a dynamic memory for capacitive data storage, enhanced storage performances are achieved by increasing the value of the storage capacitance. A junction capacitor is formed between the source...
4864374 Two-transistor dram cell with high alpha particle immunity  
A DRAM cell (8) having a storage node (18), a pass transistor (76) and a polysilicon word line (84) formed within an oxide isolated trench (68), thereby providing high soft error immunity. A write...
4858183 ECL high speed semiconductor memory and method of accessing stored information therein  
A hybrid ECL memory includes a hybrid memory array 36 which utilizes cross coupled CMOS latches (70). Each CMOS latch (70) is accessed by an ECL decoder (40) and an ECL Word Line driver (42) to...
4849934 Logic circuit using resonant-tunneling transistor  
A logic circuit including a resonant-tunneling transistor having a superlattice containing at least one quantum well layer, and a constant current source operatively connected between a base and an...
4831585 Four transistor cross-coupled bitline content addressable memory  
A content addressable memory cell comprises two storage IGFETs connected between a Match line and respective bitlines. Stored potentials are applied to the gates of the IGFETs through Write IGFETs...
4831614 Direct access storage unit using tunneling current techniques  
The storage unit comprises an array of tunnel tips (13) arranged at tunneling distance from a recording surface (2a) of a storage medium (2) which is capable of permitting digital information to be...
4831588 Integrated memory circuit having a differential read amplifier  
A monolithic integrated memory includes a differential read amplifier circuit which is associated with a column of the memory and which has two source-coupled field effect transistors, the coupling...
4829507 Method of and system for atomic scale readout of recorded information  
A recording and readout information system having atomic scale densities comprises a recording medium having a carrier and means to form a pattern of atomic particles on the surface of the carrier....
4805141 Bipolar PROM having transistors with reduced base widths  
A semiconductor device having a vertical transistor consisting of a semiconductor substrate, a first semiconductor region, and a second semiconductor region operatively functioning as a collector,...
4791610 Semiconductor memory device formed of a SOI-type transistor and a capacitor  
A semiconductor memory (DRAM) device comprises memory cells, each of which is composed of an FET and a capacitor. The FET has an SOI structure. The capacitor is composed of a dielectric layer as an...
4769767 Memory patching system  
A data processing system comprising a central processing unit, a read-only memory, a changeable read-only memory and a read-write memory. A resident computer program is stored in the read-only...
4763181 High density non-charge-sensing DRAM cell  
A non-charge-sensing high density dynamic random access memory (DRAM) cell using a trench capacitor as a vertical FET and two active field effect transistors (FETs). A particular bit line is shared...
4740917 Memory using conventional cells to perform a ram or an associative memory function  
Memory comprising a matrix of conventional Harper pnp cells and peripheral circuits which allows it to be used either as a random access memory or as an associative memory. In addition to the...
4730275 Circuit for reducing the row select voltage swing in a memory array  
A circuit reduces the row select voltage swing in a memory array, thereby reducing access time, power dissipation, disturb problems, glitches on the output, and alpha particle sensitivity. A row...
4703455 Bipolar programmable memory and method  
A non-volatile bipolar memory using the technique of comparing selectively degraded bipolar transistor's betas or base-to-emitter voltages to a non-degraded transistor's beta or base-to-emitter...
4703458 Circuit for writing bipolar memory cells  
A circuit for writing bipolar memory cells is provided that reduces power dissipation by requiring only a small voltage change on the bit lines between read and write modes. The memory circuit...
4694425 Seven transistor content addressable memory (CAM) cell  
A content addressable memory including a pair of column lines (54, 56) upon which information to be matched with the contents of said memory is placed. The memory is driven by a clock such that...
4675846 Random access memory  
A bipolar random access memory array including "end of write shut down circuit means" coupled to the write circuit means is disclosed. The "end of write shut down circuit means" is activated by and...
4669062 Two-tiered dynamic random access memory (DRAM) cell  
A dynamic random access memory (DRAM) cell has three MIS transistors arranged in a two-tiered structure with high packing density. A read select MIS transistor has source, drain and channel regions...
4654823 Read/write memory and cell constituting same  
A read/write memory cell comprises a first switch having one input which constitutes the data input-output of the cell and another input connected to a loop circuit comprises a first inverter, a...
4620297 Schmitt trigger based memory cell with assisted turn on  
A Schmitt trigger memory cell includes a storage node (20) for storage of data thereon with a current limiter resistor (22) for sinking current therefrom to a source node. A driving transistor (24)...
4611221 Solid state image pick-up device  
A solid state image pick-up device comprises a charge storage section for storing the charge corresponding to an image pattern, and a read-out section for reading out the stored charge in this...
4602352 Apparatus and method for detection of infrared radiation  
An infrared detector and method of detection based on depletion of charge stored in localized states is disclosed. The detector and method involve the determination of the depletion of charge...
4599708 Method and structure for machine data storage with simultaneous write and read  
Simultaneously timed write and read addresses for data to be respectively written to, and read from, the memory are compared to determine when there is a comparison identity. In response to such a...
4597060 EPROM array and method for fabricating  
Using a method according to one embodiment of the present invention, an EPROM array may be fabricated providing a dense EPROM array. First the polycrystalline silicon floating gates are formed and...
4596003 Semiconductor memory  
A semiconductor memory which comprises a memory section including a plurality of memory cell groups, each group including a plurality of memory cells; each of said memory cell groups including a...
4592023 Latch for storing a data bit and a store incorporating said latch  
A latch that can serve as a bit storage cell in a random-access store. The latch includes an AND gate (diodes D1 and D2) the input IN of which receives the bit to be stored and the other input of...
4575822 Method and means for data storage using tunnel current data readout  
Disclosed is a digital memory in which data is stored by establishing perturbations in a surface of a substrate and thereafter identifying the perturbations by establishing a tunnel electron...
4569036 Semiconductor dynamic memory device  
A semiconductor dynamic memory device includes a plurality of memories, row decoders for selecting the row of the memories, column decoders for selecting the column of memories, and sense amplifier...
RE32071 Resistive gate FET flip-flop storage cell  
An improved bistable FET circuit is disclosed which employs a reduced number of device elements and occupies less space in an integrated circuit. The flip-flop circuit includes the FET device...
4554645 Multi-port register implementation  
The present invention is especially directed toward a memory cell designed for use in a register stack in which multiple independent and parallel read/write and read operations may proceed...
Matches 201 - 250 out of 396 < 1 2 3 4 5 6 7 8 >