|
Match
|
Document |
Document Title |
|
|
5532956 |
Memory cell structure for semiconductor device and dynamic semiconductor memory device
A memory cell structure for a semiconductor device includes a capacitor for storing electric charge, a first transistor for controlling storage and release of charge in the capacitor, and a second...
|
|
|
5526305 |
Two-transistor dynamic random-access memory cell
A dynamic random access memory circuit for storing an information signal using both a data input line and a data output line for a two-transistor dynamic ram cell memory circuit is disclosed. The...
|
|
|
5523968 |
IC semiconductor memory devices with maintained stable operation and lower operating current characteristics
Semiconductor memory devices, such as, SRAM IC memory devices, include a shield structure for shielding load elements in the memory cells of the memory devices from electric fields generated by...
|
|
|
5515315 |
Dynamic random access memory
A dynamic random access memory, in which a connection switch circuit is provided between the output of a sense amplifier and a data bus or between memory block, which circuit is controlled in...
|
|
|
5514882 |
Bistable four layer device memory cell and method for storing and retrieving binary information
A new static memory cell based on the bistable operation of a three-terminal four layer semiconductor device working in the forward blocking state is disclosed. The power consumption of the memory...
|
|
|
5512773 |
Switching element with memory provided with Schottky tunnelling barrier
A switching element is provided with two electrodes (1, 2) with a semiconducting dielectric (3) therebetween, one electrode (2) having a material which forms a Schottky contact with the...
|
|
|
5483479 |
Associative storage memory
A memory cell for an associative storage memory device includes a transmission gate which is rendered conductive or non-conductive in response to a potential on a word line for transferring...
|
|
|
5469380 |
Semiconductor memory
A semiconductor memory having NMOS write transistors (16, 14) formed in series between a node (N1) of a memory cell (MC) and a ground level, the gate of the transistor (16) being connected to a...
|
|
|
5467267 |
PROM built-in micro computer
A PROM built-in micro computer has a semiconducting nonvolatile memory which can be written into electrically, and has a micro computer. It detects a semiconducting nonvolatile memory cell whose...
|
|
|
5467304 |
Semiconductor integrated circuit
A semiconductor integrated circuit has an identification code indicative of the classification of the product given at or after an assembling process. The semiconductor integrated circuit also...
|
|
|
5453950 |
Five transistor memory cell with shared power line
Static random access memory cells (SRAMS) containing five MOS transistors are configured in a memory array such that only three bitlines are required for two cells. A first bitline is coupled to a...
|
|
|
5453952 |
Semiconductor device having peripheral circuit formed of TFT (thin film transistor)
A semiconductor device having an increased integration density. The semiconductor device includes a memory cell array, and a peripheral circuit region formed over the memory cell array and to be in...
|
|
|
5438540 |
Semiconductor SRAM memory device
A semiconductor SRAM device is provided wherein the electrical characteristics of the memory cell of the SRAM device is enhanced by decreasing the OFF-current and by increasing ON-current of PMOS...
|
|
|
5428574 |
Static RAM with test features
A static RAM includes test features which provide for the detection of soft defects which may cause a defective SRAM cell to behave as a functional DRAM cell. Provision is made for writing either a...
|
|
|
5422841 |
Semiconductor memory device having reverse base current bipolar transistor-field effect transistor memory cell
A semiconductor memory device, which has a memory cell comprising the following transistors: a transistor for selecting; and a bipolar transistor for memorizing, which has a base region whose base...
|
|
|
5416736 |
Vertical field-effect transistor and a semiconductor memory cell having the transistor
The disclosure includes a vertical field-effect transistor (115) with a laterally recessed channel region (92), a vertical field-effect transistor (116) having a graded diffusion junction (31), a...
|
|
|
5398200 |
Vertically formed semiconductor random access memory device
A semiconductor memory device is formed having a substrate (12). A diffusion (14) is formed within the substrate (12). A first vertical transistor stack (122) is formed. A second vertical...
|
|
|
5396456 |
Fully used tub DRAM cell
A method is described for forming a dynamic random access memory cell capacitor in which a polysilicon spacer is formed on top of the bottom polysilicon electrode to construct a tub shape and a wet...
|
|
|
5386382 |
Semiconductor memory device and a manufacturing method thereof
A semiconductor memory device includes a cell array region and a peripheral circuit region, wherein a channel is formed to surround the cell array region, on a border region between the cell array...
|
|
|
5386379 |
Memory cell for associative memory
The invention relates to a memory cell for a static associative memory comprising two arrays of transistors, a first array having a data storage function and a second array having a comparison...
|
|
|
5383149 |
Ulsi mask ROM structure and method of manufacture
A ROM device provides a double density memory array. The word line array is composed of transversely disposed conductors sandwiched between two arrays of bit lines which are orthogonally disposed...
|
|
|
5379251 |
Method and apparatus for static RAM
An SRAM memory cell structure, wherein a word line is disposed near the center of a cell, each one of driver transistors is disposed on both sides thereof substantially in parallel with each other,...
|
|
|
5373476 |
Highly integrated semiconductor memory device with triple well structure
A highly integrated semiconductor memory device, such as a DRAM, is provided with a unique triple-well structure which results in reduced junction capacitance of transistors and a smaller body...
|
|
|
5365477 |
Dynamic random access memory device
A vertically integrated DRAM cell having a storage time of at least 4.5 hours at room temperature, formed from a wide-bandgap semiconductor such as GaAs or AlGaAs, in which an n-p-n bipolar access...
|
|
|
5347483 |
Non-volatile associative memory with low transistor count
A non-volatile memory cell is disclosed. The non-volatile memory cell includes first and second selecting transistors, first and second non-volatile memory transistors for storing data in a...
|
|
|
5347487 |
BICMOS latch/driver circuit, such as for a gate array memory cell
A BICMOS latch driver L/D is used to implement a BICMOS gate array memory cell (FIG. 2b). The memory cell includes a latch formed by cross-coupled invertors (INV1 and INV2). The driver stage is...
|
|
|
5341327 |
Static random access type semiconductor memory device
An object of the present invention is to miniaturize a structure of a memory cell in an SRAM. The memory cell in the SRAM includes a pair of access transistors, a pair of driver transistors and a...
|
|
|
5341326 |
Semiconductor memory having memory cell units each including cascade-connected MOS transistors
A semiconductor memory cell comprises a cascade gate including a plurality of cascade-connected MOS transistors and having one end connected to a first node, and a plurality of capacitors for data...
|
|
|
5329481 |
Semiconductor device having a memory cell
A semiconductor device with at least one programmable memory cell which includes a bipolar transistor (T 1 ) with an emitter (11) and a collector (12) of a first conductivity type and a base (10)...
|
|
|
5329487 |
Two transistor flash EPROM cell
A two-transistor flash EPROM cell includes a first floating gate transistor for programming the cell and a second merged transistor for reading the cell. The first transistor, a floating gate...
|
|
|
5325325 |
Semiconductor memory device capable of initializing storage data
An SRAM is provided wherein each memory cell has first and second storage nodes to be maintained at complementary potentials corresponding to storage data and first and second inverters provided in...
|
|
|
5311465 |
Semiconductor memory device that uses a negative differential resistance
A semiconductor memory device comprises a memory cell transistor that includes two active parts each including therein an emitter and a base and showing a negative differential resistance. The...
|
|
|
5307311 |
Microvibratory memory device
A memory device whose media scanning is vibrationally (cyclic harmonic vibration) or inertially (one-time pulsed read/write) driven is provided, comprising a plurality of cantilevers (7, 7', 7"),...
|
|
|
5299150 |
Circuit for preventing false programming of anti-fuse elements
A circuit for preventing false programming of unselected anti-fuses in an anti-fuse array includes a series impedance including a plurality of transistors which may be used for partial address...
|
|
|
5296752 |
Current memory cell
A current memory cell for sampling a current (I) at a current terminal (5) during a sample interval and for applying the current (I) to the current terminal (5) during a hold interval. A first...
|
|
|
5297089 |
Balanced bit line pull up circuitry for random access memories
A balancing circuit which may be used as part of a random access memory system for eliminating bit line offset, is disclosed. The balancing circuit contemplated by the invention is capable of...
|
|
|
5293335 |
Ceramic thin film memory device
A digital memory circuit for electronic applications. The circuit has at least one memory element connected in series with a load resistor. The digital memory circuit also includes a voltage supply...
|
|
|
5289408 |
Memory apparatus using tunnel current techniques
A scanning tunneling microscope memory apparatus comprises first and second integrated circuit (IC) substrates. First and second cantilevers, which can be moved by piezoelectric elements, are...
|
|
|
5287303 |
SCR type memory apparatus
An SCR type memory apparatus which is short in access time, easy in setting current values upon reading and writing and easy in constructing a peripheral circuit with less power supply voltage...
|
|
|
5276638 |
Bipolar memory cell with isolated PNP load
A bipolar memory array and memory cell. The memory cell has a pair of cross coupled NPN storage transistors and a pair of PNP load transistors. The collector of each of the load transistors is...
|
|
|
5255225 |
Semiconductor integrated circuit device and memory consisting of semiconductor integrated circuit
A semiconductor integrated circuit device including a level conversion circuit in which the simplifying of the circuit and the increasing of the speed of operation have been attained is provided. A...
|
|
|
5253202 |
Word line driver circuit for dynamic random access memories
A wordline driver circuit for reading the contents of a Dynamic Random Access Memory (DRAM). The circuit is implemented in CMOS and is capable of pulling the wordlines to a negative potential with...
|
|
|
5243557 |
Bi-CMOS semiconductor integrated circuit
Disclosed here in is a semiconductor integrated circuit comprising a substrate, a memory cell array having a plurality of memory cells arranged in rows and columns, a plurality of word lines, and a...
|
|
|
5235543 |
Dual port static memory with one cycle read-modify-write
A dual port static memory cell with one cycle read-modify-write operation. The static memory cell includes a write line for receiving new data to be written into the static memory cell, switching...
|
|
|
5216632 |
Memory arrangement with a read-out circuit for a static memory cell
A memory arrangement that includes a static memory cell with two MOSFETs that are connected such that an input signal for setting the memory cell is applied to one MOSFET, and the output of the...
|
|
|
5164916 |
High-density double-sided multi-string memory module with resistor for insertion detection
A high-density memory module has thirty-two memory integrated circuit chips, sixteen decoupling capacitors, and two resistors mounted on a double-sided multi-layer printed wiring board having a...
|
|
|
5162819 |
Information processing apparatus, information processing method, and recording medium employed therefor
An information processing apparatus comprises a recording medium having at least an underlying electrode and a photoconductive thin film and having an insulating or semiconducting recording region...
|
|
|
5144581 |
Apparatus including atomic probes utilizing tunnel current to read, write and erase data
A micro scanning tunneling microscope ("STM") arithmetic circuit device comprises an information-rewritable micro STM recording medium and a micro STM recording apparatus which temporarily stores...
|
|
|
5136533 |
Sidewall capacitor DRAM cell
A dynamic RAM is provided with enhanced charge storage capacity by increasing the surface area between the two electrodes of the storage capacitor. The first electrode consists of a thick...
|
|
|
5132934 |
Method and apparatus for storing digital information in the form of stored charges
Method and apparatus for storing digital information in a dense memory structure. A semiconductor substrate has a thin insulating layer formed thereon. Over the thin insulating layer is formed a...
|